cputable.c 22 KB

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  1. /*
  2. * arch/ppc/kernel/cputable.c
  3. *
  4. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #include <linux/config.h>
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <asm/cputable.h>
  17. struct cpu_spec* cur_cpu_spec[NR_CPUS];
  18. extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  19. extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  20. extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  21. extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22. extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23. extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24. extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25. extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26. extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27. extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28. extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29. extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30. extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31. #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  32. !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
  33. !defined(CONFIG_BOOKE))
  34. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  35. * ones as well...
  36. */
  37. #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  38. PPC_FEATURE_HAS_MMU)
  39. /* We only set the spe features if the kernel was compiled with
  40. * spe support
  41. */
  42. #ifdef CONFIG_SPE
  43. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  44. #else
  45. #define PPC_FEATURE_SPE_COMP 0
  46. #endif
  47. struct cpu_spec cpu_specs[] = {
  48. #if CLASSIC_PPC
  49. { /* 601 */
  50. .pvr_mask = 0xffff0000,
  51. .pvr_value = 0x00010000,
  52. .cpu_name = "601",
  53. .cpu_features = CPU_FTRS_PPC601,
  54. .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
  55. PPC_FEATURE_UNIFIED_CACHE,
  56. .icache_bsize = 32,
  57. .dcache_bsize = 32,
  58. .cpu_setup = __setup_cpu_601
  59. },
  60. { /* 603 */
  61. .pvr_mask = 0xffff0000,
  62. .pvr_value = 0x00030000,
  63. .cpu_name = "603",
  64. .cpu_features = CPU_FTRS_603,
  65. .cpu_user_features = COMMON_PPC,
  66. .icache_bsize = 32,
  67. .dcache_bsize = 32,
  68. .cpu_setup = __setup_cpu_603
  69. },
  70. { /* 603e */
  71. .pvr_mask = 0xffff0000,
  72. .pvr_value = 0x00060000,
  73. .cpu_name = "603e",
  74. .cpu_features = CPU_FTRS_603,
  75. .cpu_user_features = COMMON_PPC,
  76. .icache_bsize = 32,
  77. .dcache_bsize = 32,
  78. .cpu_setup = __setup_cpu_603
  79. },
  80. { /* 603ev */
  81. .pvr_mask = 0xffff0000,
  82. .pvr_value = 0x00070000,
  83. .cpu_name = "603ev",
  84. .cpu_features = CPU_FTRS_603,
  85. .cpu_user_features = COMMON_PPC,
  86. .icache_bsize = 32,
  87. .dcache_bsize = 32,
  88. .cpu_setup = __setup_cpu_603
  89. },
  90. { /* 604 */
  91. .pvr_mask = 0xffff0000,
  92. .pvr_value = 0x00040000,
  93. .cpu_name = "604",
  94. .cpu_features = CPU_FTRS_604,
  95. .cpu_user_features = COMMON_PPC,
  96. .icache_bsize = 32,
  97. .dcache_bsize = 32,
  98. .num_pmcs = 2,
  99. .cpu_setup = __setup_cpu_604
  100. },
  101. { /* 604e */
  102. .pvr_mask = 0xfffff000,
  103. .pvr_value = 0x00090000,
  104. .cpu_name = "604e",
  105. .cpu_features = CPU_FTRS_604,
  106. .cpu_user_features = COMMON_PPC,
  107. .icache_bsize = 32,
  108. .dcache_bsize = 32,
  109. .num_pmcs = 4,
  110. .cpu_setup = __setup_cpu_604
  111. },
  112. { /* 604r */
  113. .pvr_mask = 0xffff0000,
  114. .pvr_value = 0x00090000,
  115. .cpu_name = "604r",
  116. .cpu_features = CPU_FTRS_604,
  117. .cpu_user_features = COMMON_PPC,
  118. .icache_bsize = 32,
  119. .dcache_bsize = 32,
  120. .num_pmcs = 4,
  121. .cpu_setup = __setup_cpu_604
  122. },
  123. { /* 604ev */
  124. .pvr_mask = 0xffff0000,
  125. .pvr_value = 0x000a0000,
  126. .cpu_name = "604ev",
  127. .cpu_features = CPU_FTRS_604,
  128. .cpu_user_features = COMMON_PPC,
  129. .icache_bsize = 32,
  130. .dcache_bsize = 32,
  131. .num_pmcs = 4,
  132. .cpu_setup = __setup_cpu_604
  133. },
  134. { /* 740/750 (0x4202, don't support TAU ?) */
  135. .pvr_mask = 0xffffffff,
  136. .pvr_value = 0x00084202,
  137. .cpu_name = "740/750",
  138. .cpu_features = CPU_FTRS_740_NOTAU,
  139. .cpu_user_features = COMMON_PPC,
  140. .icache_bsize = 32,
  141. .dcache_bsize = 32,
  142. .num_pmcs = 4,
  143. .cpu_setup = __setup_cpu_750
  144. },
  145. { /* 750CX (80100 and 8010x?) */
  146. .pvr_mask = 0xfffffff0,
  147. .pvr_value = 0x00080100,
  148. .cpu_name = "750CX",
  149. .cpu_features = CPU_FTRS_750,
  150. .cpu_user_features = COMMON_PPC,
  151. .icache_bsize = 32,
  152. .dcache_bsize = 32,
  153. .num_pmcs = 4,
  154. .cpu_setup = __setup_cpu_750cx
  155. },
  156. { /* 750CX (82201 and 82202) */
  157. .pvr_mask = 0xfffffff0,
  158. .pvr_value = 0x00082200,
  159. .cpu_name = "750CX",
  160. .cpu_features = CPU_FTRS_750,
  161. .cpu_user_features = COMMON_PPC,
  162. .icache_bsize = 32,
  163. .dcache_bsize = 32,
  164. .num_pmcs = 4,
  165. .cpu_setup = __setup_cpu_750cx
  166. },
  167. { /* 750CXe (82214) */
  168. .pvr_mask = 0xfffffff0,
  169. .pvr_value = 0x00082210,
  170. .cpu_name = "750CXe",
  171. .cpu_features = CPU_FTRS_750,
  172. .cpu_user_features = COMMON_PPC,
  173. .icache_bsize = 32,
  174. .dcache_bsize = 32,
  175. .num_pmcs = 4,
  176. .cpu_setup = __setup_cpu_750cx
  177. },
  178. { /* 750CXe "Gekko" (83214) */
  179. .pvr_mask = 0xffffffff,
  180. .pvr_value = 0x00083214,
  181. .cpu_name = "750CXe",
  182. .cpu_features = CPU_FTRS_750,
  183. .cpu_user_features = COMMON_PPC,
  184. .icache_bsize = 32,
  185. .dcache_bsize = 32,
  186. .num_pmcs = 4,
  187. .cpu_setup = __setup_cpu_750cx
  188. },
  189. { /* 745/755 */
  190. .pvr_mask = 0xfffff000,
  191. .pvr_value = 0x00083000,
  192. .cpu_name = "745/755",
  193. .cpu_features = CPU_FTRS_750,
  194. .cpu_user_features = COMMON_PPC,
  195. .icache_bsize = 32,
  196. .dcache_bsize = 32,
  197. .num_pmcs = 4,
  198. .cpu_setup = __setup_cpu_750
  199. },
  200. { /* 750FX rev 1.x */
  201. .pvr_mask = 0xffffff00,
  202. .pvr_value = 0x70000100,
  203. .cpu_name = "750FX",
  204. .cpu_features = CPU_FTRS_750FX1,
  205. .cpu_user_features = COMMON_PPC,
  206. .icache_bsize = 32,
  207. .dcache_bsize = 32,
  208. .num_pmcs = 4,
  209. .cpu_setup = __setup_cpu_750
  210. },
  211. { /* 750FX rev 2.0 must disable HID0[DPM] */
  212. .pvr_mask = 0xffffffff,
  213. .pvr_value = 0x70000200,
  214. .cpu_name = "750FX",
  215. .cpu_features = CPU_FTRS_750FX2,
  216. .cpu_user_features = COMMON_PPC,
  217. .icache_bsize = 32,
  218. .dcache_bsize = 32,
  219. .num_pmcs = 4,
  220. .cpu_setup = __setup_cpu_750
  221. },
  222. { /* 750FX (All revs except 2.0) */
  223. .pvr_mask = 0xffff0000,
  224. .pvr_value = 0x70000000,
  225. .cpu_name = "750FX",
  226. .cpu_features = CPU_FTRS_750FX,
  227. .cpu_user_features = COMMON_PPC,
  228. .icache_bsize = 32,
  229. .dcache_bsize = 32,
  230. .num_pmcs = 4,
  231. .cpu_setup = __setup_cpu_750fx
  232. },
  233. { /* 750GX */
  234. .pvr_mask = 0xffff0000,
  235. .pvr_value = 0x70020000,
  236. .cpu_name = "750GX",
  237. .cpu_features = CPU_FTRS_750GX,
  238. .cpu_user_features = COMMON_PPC,
  239. .icache_bsize = 32,
  240. .dcache_bsize = 32,
  241. .num_pmcs = 4,
  242. .cpu_setup = __setup_cpu_750fx
  243. },
  244. { /* 740/750 (L2CR bit need fixup for 740) */
  245. .pvr_mask = 0xffff0000,
  246. .pvr_value = 0x00080000,
  247. .cpu_name = "740/750",
  248. .cpu_features = CPU_FTRS_740,
  249. .cpu_user_features = COMMON_PPC,
  250. .icache_bsize = 32,
  251. .dcache_bsize = 32,
  252. .num_pmcs = 4,
  253. .cpu_setup = __setup_cpu_750
  254. },
  255. { /* 7400 rev 1.1 ? (no TAU) */
  256. .pvr_mask = 0xffffffff,
  257. .pvr_value = 0x000c1101,
  258. .cpu_name = "7400 (1.1)",
  259. .cpu_features = CPU_FTRS_7400_NOTAU,
  260. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  261. .icache_bsize = 32,
  262. .dcache_bsize = 32,
  263. .num_pmcs = 4,
  264. .cpu_setup = __setup_cpu_7400
  265. },
  266. { /* 7400 */
  267. .pvr_mask = 0xffff0000,
  268. .pvr_value = 0x000c0000,
  269. .cpu_name = "7400",
  270. .cpu_features = CPU_FTRS_7400,
  271. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  272. .icache_bsize = 32,
  273. .dcache_bsize = 32,
  274. .num_pmcs = 4,
  275. .cpu_setup = __setup_cpu_7400
  276. },
  277. { /* 7410 */
  278. .pvr_mask = 0xffff0000,
  279. .pvr_value = 0x800c0000,
  280. .cpu_name = "7410",
  281. .cpu_features = CPU_FTRS_7400,
  282. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  283. .icache_bsize = 32,
  284. .dcache_bsize = 32,
  285. .num_pmcs = 4,
  286. .cpu_setup = __setup_cpu_7410
  287. },
  288. { /* 7450 2.0 - no doze/nap */
  289. .pvr_mask = 0xffffffff,
  290. .pvr_value = 0x80000200,
  291. .cpu_name = "7450",
  292. .cpu_features = CPU_FTRS_7450_20,
  293. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  294. .icache_bsize = 32,
  295. .dcache_bsize = 32,
  296. .num_pmcs = 6,
  297. .cpu_setup = __setup_cpu_745x
  298. },
  299. { /* 7450 2.1 */
  300. .pvr_mask = 0xffffffff,
  301. .pvr_value = 0x80000201,
  302. .cpu_name = "7450",
  303. .cpu_features = CPU_FTRS_7450_21,
  304. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  305. .icache_bsize = 32,
  306. .dcache_bsize = 32,
  307. .num_pmcs = 6,
  308. .cpu_setup = __setup_cpu_745x
  309. },
  310. { /* 7450 2.3 and newer */
  311. .pvr_mask = 0xffff0000,
  312. .pvr_value = 0x80000000,
  313. .cpu_name = "7450",
  314. .cpu_features = CPU_FTRS_7450_23,
  315. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  316. .icache_bsize = 32,
  317. .dcache_bsize = 32,
  318. .num_pmcs = 6,
  319. .cpu_setup = __setup_cpu_745x
  320. },
  321. { /* 7455 rev 1.x */
  322. .pvr_mask = 0xffffff00,
  323. .pvr_value = 0x80010100,
  324. .cpu_name = "7455",
  325. .cpu_features = CPU_FTRS_7455_1,
  326. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  327. .icache_bsize = 32,
  328. .dcache_bsize = 32,
  329. .num_pmcs = 6,
  330. .cpu_setup = __setup_cpu_745x
  331. },
  332. { /* 7455 rev 2.0 */
  333. .pvr_mask = 0xffffffff,
  334. .pvr_value = 0x80010200,
  335. .cpu_name = "7455",
  336. .cpu_features = CPU_FTRS_7455_20,
  337. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  338. .icache_bsize = 32,
  339. .dcache_bsize = 32,
  340. .num_pmcs = 6,
  341. .cpu_setup = __setup_cpu_745x
  342. },
  343. { /* 7455 others */
  344. .pvr_mask = 0xffff0000,
  345. .pvr_value = 0x80010000,
  346. .cpu_name = "7455",
  347. .cpu_features = CPU_FTRS_7455,
  348. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  349. .icache_bsize = 32,
  350. .dcache_bsize = 32,
  351. .num_pmcs = 6,
  352. .cpu_setup = __setup_cpu_745x
  353. },
  354. { /* 7447/7457 Rev 1.0 */
  355. .pvr_mask = 0xffffffff,
  356. .pvr_value = 0x80020100,
  357. .cpu_name = "7447/7457",
  358. .cpu_features = CPU_FTRS_7447_10,
  359. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  360. .icache_bsize = 32,
  361. .dcache_bsize = 32,
  362. .num_pmcs = 6,
  363. .cpu_setup = __setup_cpu_745x
  364. },
  365. { /* 7447/7457 Rev 1.1 */
  366. .pvr_mask = 0xffffffff,
  367. .pvr_value = 0x80020101,
  368. .cpu_name = "7447/7457",
  369. .cpu_features = CPU_FTRS_7447_10,
  370. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  371. .icache_bsize = 32,
  372. .dcache_bsize = 32,
  373. .num_pmcs = 6,
  374. .cpu_setup = __setup_cpu_745x
  375. },
  376. { /* 7447/7457 Rev 1.2 and later */
  377. .pvr_mask = 0xffff0000,
  378. .pvr_value = 0x80020000,
  379. .cpu_name = "7447/7457",
  380. .cpu_features = CPU_FTRS_7447,
  381. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  382. .icache_bsize = 32,
  383. .dcache_bsize = 32,
  384. .num_pmcs = 6,
  385. .cpu_setup = __setup_cpu_745x
  386. },
  387. { /* 7447A */
  388. .pvr_mask = 0xffff0000,
  389. .pvr_value = 0x80030000,
  390. .cpu_name = "7447A",
  391. .cpu_features = CPU_FTRS_7447A,
  392. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  393. .icache_bsize = 32,
  394. .dcache_bsize = 32,
  395. .num_pmcs = 6,
  396. .cpu_setup = __setup_cpu_745x
  397. },
  398. { /* 7448 */
  399. .pvr_mask = 0xffff0000,
  400. .pvr_value = 0x80040000,
  401. .cpu_name = "7448",
  402. .cpu_features = CPU_FTRS_7447A,
  403. .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
  404. .icache_bsize = 32,
  405. .dcache_bsize = 32,
  406. .num_pmcs = 6,
  407. .cpu_setup = __setup_cpu_745x
  408. },
  409. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  410. .pvr_mask = 0x7fff0000,
  411. .pvr_value = 0x00810000,
  412. .cpu_name = "82xx",
  413. .cpu_features = CPU_FTRS_82XX,
  414. .cpu_user_features = COMMON_PPC,
  415. .icache_bsize = 32,
  416. .dcache_bsize = 32,
  417. .cpu_setup = __setup_cpu_603
  418. },
  419. { /* All G2_LE (603e core, plus some) have the same pvr */
  420. .pvr_mask = 0x7fff0000,
  421. .pvr_value = 0x00820000,
  422. .cpu_name = "G2_LE",
  423. .cpu_features = CPU_FTRS_G2_LE,
  424. .cpu_user_features = COMMON_PPC,
  425. .icache_bsize = 32,
  426. .dcache_bsize = 32,
  427. .cpu_setup = __setup_cpu_603
  428. },
  429. { /* e300 (a 603e core, plus some) on 83xx */
  430. .pvr_mask = 0x7fff0000,
  431. .pvr_value = 0x00830000,
  432. .cpu_name = "e300",
  433. .cpu_features = CPU_FTRS_E300,
  434. .cpu_user_features = COMMON_PPC,
  435. .icache_bsize = 32,
  436. .dcache_bsize = 32,
  437. .cpu_setup = __setup_cpu_603
  438. },
  439. { /* default match, we assume split I/D cache & TB (non-601)... */
  440. .pvr_mask = 0x00000000,
  441. .pvr_value = 0x00000000,
  442. .cpu_name = "(generic PPC)",
  443. .cpu_features = CPU_FTRS_CLASSIC32,
  444. .cpu_user_features = COMMON_PPC,
  445. .icache_bsize = 32,
  446. .dcache_bsize = 32,
  447. .cpu_setup = __setup_cpu_generic
  448. },
  449. #endif /* CLASSIC_PPC */
  450. #ifdef CONFIG_PPC64BRIDGE
  451. { /* Power3 */
  452. .pvr_mask = 0xffff0000,
  453. .pvr_value = 0x00400000,
  454. .cpu_name = "Power3 (630)",
  455. .cpu_features = CPU_FTRS_POWER3_32,
  456. .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
  457. .icache_bsize = 128,
  458. .dcache_bsize = 128,
  459. .num_pmcs = 8,
  460. .cpu_setup = __setup_cpu_power3
  461. },
  462. { /* Power3+ */
  463. .pvr_mask = 0xffff0000,
  464. .pvr_value = 0x00410000,
  465. .cpu_name = "Power3 (630+)",
  466. .cpu_features = CPU_FTRS_POWER3_32,
  467. .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
  468. .icache_bsize = 128,
  469. .dcache_bsize = 128,
  470. .num_pmcs = 8,
  471. .cpu_setup = __setup_cpu_power3
  472. },
  473. { /* I-star */
  474. .pvr_mask = 0xffff0000,
  475. .pvr_value = 0x00360000,
  476. .cpu_name = "I-star",
  477. .cpu_features = CPU_FTRS_POWER3_32,
  478. .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
  479. .icache_bsize = 128,
  480. .dcache_bsize = 128,
  481. .num_pmcs = 8,
  482. .cpu_setup = __setup_cpu_power3
  483. },
  484. { /* S-star */
  485. .pvr_mask = 0xffff0000,
  486. .pvr_value = 0x00370000,
  487. .cpu_name = "S-star",
  488. .cpu_features = CPU_FTRS_POWER3_32,
  489. .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
  490. .icache_bsize = 128,
  491. .dcache_bsize = 128,
  492. .num_pmcs = 8,
  493. .cpu_setup = __setup_cpu_power3
  494. },
  495. #endif /* CONFIG_PPC64BRIDGE */
  496. #ifdef CONFIG_POWER4
  497. { /* PPC970FX */
  498. .pvr_mask = 0xffff0000,
  499. .pvr_value = 0x003c0000,
  500. .cpu_name = "PPC970FX",
  501. .cpu_features = CPU_FTRS_970_32,
  502. .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
  503. .icache_bsize = 128,
  504. .dcache_bsize = 128,
  505. .num_pmcs = 8,
  506. .cpu_setup = __setup_cpu_ppc970
  507. },
  508. #endif /* CONFIG_POWER4 */
  509. #ifdef CONFIG_8xx
  510. { /* 8xx */
  511. .pvr_mask = 0xffff0000,
  512. .pvr_value = 0x00500000,
  513. .cpu_name = "8xx",
  514. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  515. * if the 8xx code is there.... */
  516. .cpu_features = CPU_FTRS_8XX,
  517. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  518. .icache_bsize = 16,
  519. .dcache_bsize = 16,
  520. },
  521. #endif /* CONFIG_8xx */
  522. #ifdef CONFIG_40x
  523. { /* 403GC */
  524. .pvr_mask = 0xffffff00,
  525. .pvr_value = 0x00200200,
  526. .cpu_name = "403GC",
  527. .cpu_features = CPU_FTRS_40X,
  528. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  529. .icache_bsize = 16,
  530. .dcache_bsize = 16,
  531. },
  532. { /* 403GCX */
  533. .pvr_mask = 0xffffff00,
  534. .pvr_value = 0x00201400,
  535. .cpu_name = "403GCX",
  536. .cpu_features = CPU_FTRS_40X,
  537. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  538. .icache_bsize = 16,
  539. .dcache_bsize = 16,
  540. },
  541. { /* 403G ?? */
  542. .pvr_mask = 0xffff0000,
  543. .pvr_value = 0x00200000,
  544. .cpu_name = "403G ??",
  545. .cpu_features = CPU_FTRS_40X,
  546. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  547. .icache_bsize = 16,
  548. .dcache_bsize = 16,
  549. },
  550. { /* 405GP */
  551. .pvr_mask = 0xffff0000,
  552. .pvr_value = 0x40110000,
  553. .cpu_name = "405GP",
  554. .cpu_features = CPU_FTRS_40X,
  555. .cpu_user_features = PPC_FEATURE_32 |
  556. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  557. .icache_bsize = 32,
  558. .dcache_bsize = 32,
  559. },
  560. { /* STB 03xxx */
  561. .pvr_mask = 0xffff0000,
  562. .pvr_value = 0x40130000,
  563. .cpu_name = "STB03xxx",
  564. .cpu_features = CPU_FTRS_40X,
  565. .cpu_user_features = PPC_FEATURE_32 |
  566. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  567. .icache_bsize = 32,
  568. .dcache_bsize = 32,
  569. },
  570. { /* STB 04xxx */
  571. .pvr_mask = 0xffff0000,
  572. .pvr_value = 0x41810000,
  573. .cpu_name = "STB04xxx",
  574. .cpu_features = CPU_FTRS_40X,
  575. .cpu_user_features = PPC_FEATURE_32 |
  576. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  577. .icache_bsize = 32,
  578. .dcache_bsize = 32,
  579. },
  580. { /* NP405L */
  581. .pvr_mask = 0xffff0000,
  582. .pvr_value = 0x41610000,
  583. .cpu_name = "NP405L",
  584. .cpu_features = CPU_FTRS_40X,
  585. .cpu_user_features = PPC_FEATURE_32 |
  586. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  587. .icache_bsize = 32,
  588. .dcache_bsize = 32,
  589. },
  590. { /* NP4GS3 */
  591. .pvr_mask = 0xffff0000,
  592. .pvr_value = 0x40B10000,
  593. .cpu_name = "NP4GS3",
  594. .cpu_features = CPU_FTRS_40X,
  595. .cpu_user_features = PPC_FEATURE_32 |
  596. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  597. .icache_bsize = 32,
  598. .dcache_bsize = 32,
  599. },
  600. { /* NP405H */
  601. .pvr_mask = 0xffff0000,
  602. .pvr_value = 0x41410000,
  603. .cpu_name = "NP405H",
  604. .cpu_features = CPU_FTRS_40X,
  605. .cpu_user_features = PPC_FEATURE_32 |
  606. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  607. .icache_bsize = 32,
  608. .dcache_bsize = 32,
  609. },
  610. { /* 405GPr */
  611. .pvr_mask = 0xffff0000,
  612. .pvr_value = 0x50910000,
  613. .cpu_name = "405GPr",
  614. .cpu_features = CPU_FTRS_40X,
  615. .cpu_user_features = PPC_FEATURE_32 |
  616. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  617. .icache_bsize = 32,
  618. .dcache_bsize = 32,
  619. },
  620. { /* STBx25xx */
  621. .pvr_mask = 0xffff0000,
  622. .pvr_value = 0x51510000,
  623. .cpu_name = "STBx25xx",
  624. .cpu_features = CPU_FTRS_40X,
  625. .cpu_user_features = PPC_FEATURE_32 |
  626. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  627. .icache_bsize = 32,
  628. .dcache_bsize = 32,
  629. },
  630. { /* 405LP */
  631. .pvr_mask = 0xffff0000,
  632. .pvr_value = 0x41F10000,
  633. .cpu_name = "405LP",
  634. .cpu_features = CPU_FTRS_40X,
  635. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  636. .icache_bsize = 32,
  637. .dcache_bsize = 32,
  638. },
  639. { /* Xilinx Virtex-II Pro */
  640. .pvr_mask = 0xffff0000,
  641. .pvr_value = 0x20010000,
  642. .cpu_name = "Virtex-II Pro",
  643. .cpu_features = CPU_FTRS_40X,
  644. .cpu_user_features = PPC_FEATURE_32 |
  645. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  646. .icache_bsize = 32,
  647. .dcache_bsize = 32,
  648. },
  649. { /* 405EP */
  650. .pvr_mask = 0xffff0000,
  651. .pvr_value = 0x51210000,
  652. .cpu_name = "405EP",
  653. .cpu_features = CPU_FTRS_40X,
  654. .cpu_user_features = PPC_FEATURE_32 |
  655. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  656. .icache_bsize = 32,
  657. .dcache_bsize = 32,
  658. },
  659. #endif /* CONFIG_40x */
  660. #ifdef CONFIG_44x
  661. {
  662. .pvr_mask = 0xf0000fff,
  663. .pvr_value = 0x40000850,
  664. .cpu_name = "440EP Rev. A",
  665. .cpu_features = CPU_FTRS_44X,
  666. .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
  667. .icache_bsize = 32,
  668. .dcache_bsize = 32,
  669. },
  670. {
  671. .pvr_mask = 0xf0000fff,
  672. .pvr_value = 0x400008d3,
  673. .cpu_name = "440EP Rev. B",
  674. .cpu_features = CPU_FTRS_44X,
  675. .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
  676. .icache_bsize = 32,
  677. .dcache_bsize = 32,
  678. },
  679. { /* 440GP Rev. B */
  680. .pvr_mask = 0xf0000fff,
  681. .pvr_value = 0x40000440,
  682. .cpu_name = "440GP Rev. B",
  683. .cpu_features = CPU_FTRS_44X,
  684. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  685. .icache_bsize = 32,
  686. .dcache_bsize = 32,
  687. },
  688. { /* 440GP Rev. C */
  689. .pvr_mask = 0xf0000fff,
  690. .pvr_value = 0x40000481,
  691. .cpu_name = "440GP Rev. C",
  692. .cpu_features = CPU_FTRS_44X,
  693. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  694. .icache_bsize = 32,
  695. .dcache_bsize = 32,
  696. },
  697. { /* 440GX Rev. A */
  698. .pvr_mask = 0xf0000fff,
  699. .pvr_value = 0x50000850,
  700. .cpu_name = "440GX Rev. A",
  701. .cpu_features = CPU_FTRS_44X,
  702. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  703. .icache_bsize = 32,
  704. .dcache_bsize = 32,
  705. },
  706. { /* 440GX Rev. B */
  707. .pvr_mask = 0xf0000fff,
  708. .pvr_value = 0x50000851,
  709. .cpu_name = "440GX Rev. B",
  710. .cpu_features = CPU_FTRS_44X,
  711. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  712. .icache_bsize = 32,
  713. .dcache_bsize = 32,
  714. },
  715. { /* 440GX Rev. C */
  716. .pvr_mask = 0xf0000fff,
  717. .pvr_value = 0x50000892,
  718. .cpu_name = "440GX Rev. C",
  719. .cpu_features = CPU_FTRS_44X,
  720. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  721. .icache_bsize = 32,
  722. .dcache_bsize = 32,
  723. },
  724. { /* 440GX Rev. F */
  725. .pvr_mask = 0xf0000fff,
  726. .pvr_value = 0x50000894,
  727. .cpu_name = "440GX Rev. F",
  728. .cpu_features = CPU_FTRS_44X,
  729. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  730. .icache_bsize = 32,
  731. .dcache_bsize = 32,
  732. },
  733. { /* 440SP Rev. A */
  734. .pvr_mask = 0xff000fff,
  735. .pvr_value = 0x53000891,
  736. .cpu_name = "440SP Rev. A",
  737. .cpu_features = CPU_FTRS_44X,
  738. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  739. .icache_bsize = 32,
  740. .dcache_bsize = 32,
  741. },
  742. #endif /* CONFIG_44x */
  743. #ifdef CONFIG_FSL_BOOKE
  744. { /* e200z5 */
  745. .pvr_mask = 0xfff00000,
  746. .pvr_value = 0x81000000,
  747. .cpu_name = "e200z5",
  748. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  749. .cpu_features = CPU_FTRS_E200,
  750. .cpu_user_features = PPC_FEATURE_32 |
  751. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
  752. PPC_FEATURE_UNIFIED_CACHE,
  753. .dcache_bsize = 32,
  754. },
  755. { /* e200z6 */
  756. .pvr_mask = 0xfff00000,
  757. .pvr_value = 0x81100000,
  758. .cpu_name = "e200z6",
  759. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  760. .cpu_features = CPU_FTRS_E200,
  761. .cpu_user_features = PPC_FEATURE_32 |
  762. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  763. PPC_FEATURE_HAS_EFP_SINGLE |
  764. PPC_FEATURE_UNIFIED_CACHE,
  765. .dcache_bsize = 32,
  766. },
  767. { /* e500 */
  768. .pvr_mask = 0xffff0000,
  769. .pvr_value = 0x80200000,
  770. .cpu_name = "e500",
  771. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  772. .cpu_features = CPU_FTRS_E500,
  773. .cpu_user_features = PPC_FEATURE_32 |
  774. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  775. PPC_FEATURE_HAS_EFP_SINGLE,
  776. .icache_bsize = 32,
  777. .dcache_bsize = 32,
  778. .num_pmcs = 4,
  779. },
  780. { /* e500v2 */
  781. .pvr_mask = 0xffff0000,
  782. .pvr_value = 0x80210000,
  783. .cpu_name = "e500v2",
  784. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  785. .cpu_features = CPU_FTRS_E500_2,
  786. .cpu_user_features = PPC_FEATURE_32 |
  787. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  788. PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
  789. .icache_bsize = 32,
  790. .dcache_bsize = 32,
  791. .num_pmcs = 4,
  792. },
  793. #endif
  794. #if !CLASSIC_PPC
  795. { /* default match */
  796. .pvr_mask = 0x00000000,
  797. .pvr_value = 0x00000000,
  798. .cpu_name = "(generic PPC)",
  799. .cpu_features = CPU_FTRS_GENERIC_32,
  800. .cpu_user_features = PPC_FEATURE_32,
  801. .icache_bsize = 32,
  802. .dcache_bsize = 32,
  803. }
  804. #endif /* !CLASSIC_PPC */
  805. };