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@@ -22,6 +22,7 @@
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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+#include <video/vga.h>
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#include <video/trident.h>
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#include <video/trident.h>
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#define VERSION "0.7.9-NEWAPI"
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#define VERSION "0.7.9-NEWAPI"
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@@ -149,8 +150,6 @@ static int iscyber(int id)
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}
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}
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}
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}
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-#define CRT 0x3D0 /* CRTC registers offset for color display */
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-
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static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
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static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
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{
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{
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fb_writeb(val, p->io_virt + reg);
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fb_writeb(val, p->io_virt + reg);
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@@ -525,60 +524,41 @@ static void tridentfb_copyarea(struct fb_info *info,
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static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
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static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
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{
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{
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- writeb(reg, par->io_virt + CRT + 4);
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- return readb(par->io_virt + CRT + 5);
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+ return vga_mm_rcrt(par->io_virt, reg);
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}
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}
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static inline void write3X4(struct tridentfb_par *par, int reg,
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static inline void write3X4(struct tridentfb_par *par, int reg,
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unsigned char val)
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unsigned char val)
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{
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{
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- writeb(reg, par->io_virt + CRT + 4);
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- writeb(val, par->io_virt + CRT + 5);
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-}
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-
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-static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
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-{
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- t_outb(par, reg, 0x3C4);
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- return t_inb(par, 0x3C5);
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-}
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-
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-static inline void write3C4(struct tridentfb_par *par, int reg,
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- unsigned char val)
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-{
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- t_outb(par, reg, 0x3C4);
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- t_outb(par, val, 0x3C5);
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+ vga_mm_wcrt(par->io_virt, reg, val);
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}
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}
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-static inline unsigned char read3CE(struct tridentfb_par *par, int reg)
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+static inline unsigned char read3CE(struct tridentfb_par *par,
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+ unsigned char reg)
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{
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{
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- t_outb(par, reg, 0x3CE);
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- return t_inb(par, 0x3CF);
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+ return vga_mm_rgfx(par->io_virt, reg);
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}
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}
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static inline void writeAttr(struct tridentfb_par *par, int reg,
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static inline void writeAttr(struct tridentfb_par *par, int reg,
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unsigned char val)
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unsigned char val)
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{
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{
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- fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
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- t_outb(par, reg, 0x3C0);
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- t_outb(par, val, 0x3C0);
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+ fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
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+ vga_mm_wattr(par->io_virt, reg, val);
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}
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}
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static inline void write3CE(struct tridentfb_par *par, int reg,
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static inline void write3CE(struct tridentfb_par *par, int reg,
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unsigned char val)
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unsigned char val)
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{
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{
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- t_outb(par, reg, 0x3CE);
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- t_outb(par, val, 0x3CF);
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+ vga_mm_wgfx(par->io_virt, reg, val);
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}
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}
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static void enable_mmio(void)
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static void enable_mmio(void)
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{
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{
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/* Goto New Mode */
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/* Goto New Mode */
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- outb(0x0B, 0x3C4);
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- inb(0x3C5);
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+ vga_io_rseq(0x0B);
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/* Unprotect registers */
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/* Unprotect registers */
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- outb(NewMode1, 0x3C4);
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- outb(0x80, 0x3C5);
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+ vga_io_wseq(NewMode1, 0x80);
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/* Enable MMIO */
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/* Enable MMIO */
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outb(PCIReg, 0x3D4);
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outb(PCIReg, 0x3D4);
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@@ -588,12 +568,10 @@ static void enable_mmio(void)
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static void disable_mmio(struct tridentfb_par *par)
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static void disable_mmio(struct tridentfb_par *par)
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{
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{
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/* Goto New Mode */
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/* Goto New Mode */
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- t_outb(par, 0x0B, 0x3C4);
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- t_inb(par, 0x3C5);
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+ vga_mm_rseq(par->io_virt, 0x0B);
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/* Unprotect registers */
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/* Unprotect registers */
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- t_outb(par, NewMode1, 0x3C4);
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- t_outb(par, 0x80, 0x3C5);
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+ vga_mm_wseq(par->io_virt, NewMode1, 0x80);
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/* Disable MMIO */
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/* Disable MMIO */
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t_outb(par, PCIReg, 0x3D4);
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t_outb(par, PCIReg, 0x3D4);
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@@ -602,7 +580,8 @@ static void disable_mmio(struct tridentfb_par *par)
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static void crtc_unlock(struct tridentfb_par *par)
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static void crtc_unlock(struct tridentfb_par *par)
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{
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{
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- write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F);
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+ write3X4(par, VGA_CRTC_V_SYNC_END,
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+ read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
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}
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}
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/* Return flat panel's maximum x resolution */
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/* Return flat panel's maximum x resolution */
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@@ -641,7 +620,7 @@ static int __devinit get_nativex(struct tridentfb_par *par)
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/* Set pitch */
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/* Set pitch */
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static void set_lwidth(struct tridentfb_par *par, int width)
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static void set_lwidth(struct tridentfb_par *par, int width)
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{
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{
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- write3X4(par, Offset, width & 0xFF);
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+ write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
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write3X4(par, AddColReg,
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write3X4(par, AddColReg,
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(read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
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(read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
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}
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}
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@@ -668,8 +647,8 @@ static void screen_center(struct tridentfb_par *par)
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static void set_screen_start(struct tridentfb_par *par, int base)
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static void set_screen_start(struct tridentfb_par *par, int base)
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{
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{
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u8 tmp;
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u8 tmp;
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- write3X4(par, StartAddrLow, base & 0xFF);
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- write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8);
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+ write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
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+ write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
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tmp = read3X4(par, CRTCModuleTest) & 0xDF;
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tmp = read3X4(par, CRTCModuleTest) & 0xDF;
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write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
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write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
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tmp = read3X4(par, CRTHiOrd) & 0xF8;
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tmp = read3X4(par, CRTHiOrd) & 0xF8;
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@@ -698,8 +677,8 @@ static void set_vclk(struct tridentfb_par *par, unsigned long freq)
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break;
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break;
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}
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}
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if (is3Dchip(par->chip_id)) {
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if (is3Dchip(par->chip_id)) {
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- write3C4(par, ClockHigh, hi);
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- write3C4(par, ClockLow, lo);
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+ vga_mm_wseq(par->io_virt, ClockHigh, hi);
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+ vga_mm_wseq(par->io_virt, ClockLow, lo);
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} else {
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} else {
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outb(lo, 0x43C8);
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outb(lo, 0x43C8);
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outb(hi, 0x43C9);
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outb(hi, 0x43C9);
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@@ -782,7 +761,7 @@ static unsigned int __devinit get_memsize(struct tridentfb_par *par)
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break;
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break;
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case 0x0E: /* XP */
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case 0x0E: /* XP */
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- tmp2 = read3C4(par, 0xC1);
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+ tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
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switch (tmp2) {
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switch (tmp2) {
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case 0x00:
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case 0x00:
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k = 20 * Mb;
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k = 20 * Mb;
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@@ -931,7 +910,7 @@ static int tridentfb_set_par(struct fb_info *info)
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* than requested resolution decide whether
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* than requested resolution decide whether
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* we stretch or center
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* we stretch or center
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*/
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*/
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- t_outb(par, 0xEB, 0x3C2);
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+ t_outb(par, 0xEB, VGA_MIS_W);
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shadowmode_on(par);
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shadowmode_on(par);
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@@ -941,26 +920,26 @@ static int tridentfb_set_par(struct fb_info *info)
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screen_stretch(par);
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screen_stretch(par);
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} else {
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} else {
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- t_outb(par, 0x2B, 0x3C2);
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+ t_outb(par, 0x2B, VGA_MIS_W);
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write3CE(par, CyberControl, 8);
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write3CE(par, CyberControl, 8);
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}
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}
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/* vertical timing values */
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/* vertical timing values */
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- write3X4(par, CRTVTotal, vtotal & 0xFF);
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- write3X4(par, CRTVDispEnd, vdispend & 0xFF);
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- write3X4(par, CRTVSyncStart, vsyncstart & 0xFF);
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- write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F));
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- write3X4(par, CRTVBlankStart, vblankstart & 0xFF);
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- write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */);
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+ write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
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+ write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
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+ write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
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+ write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
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+ write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
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+ write3X4(par, VGA_CRTC_V_BLANK_END, 0 /* p->vblankend & 0xFF */);
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/* horizontal timing values */
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/* horizontal timing values */
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- write3X4(par, CRTHTotal, htotal & 0xFF);
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- write3X4(par, CRTHDispEnd, hdispend & 0xFF);
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- write3X4(par, CRTHSyncStart, hsyncstart & 0xFF);
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- write3X4(par, CRTHSyncEnd,
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+ write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
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+ write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
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+ write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
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+ write3X4(par, VGA_CRTC_H_SYNC_END,
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(hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
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(hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
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- write3X4(par, CRTHBlankStart, hblankstart & 0xFF);
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- write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */);
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+ write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
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+ write3X4(par, VGA_CRTC_H_BLANK_END, 0 /* (p->hblankend & 0x1F) */);
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/* higher bits of vertical timing values */
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/* higher bits of vertical timing values */
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tmp = 0x10;
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tmp = 0x10;
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@@ -972,7 +951,7 @@ static int tridentfb_set_par(struct fb_info *info)
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if (vtotal & 0x200) tmp |= 0x20;
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if (vtotal & 0x200) tmp |= 0x20;
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if (vdispend & 0x200) tmp |= 0x40;
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if (vdispend & 0x200) tmp |= 0x40;
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if (vsyncstart & 0x200) tmp |= 0x80;
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if (vsyncstart & 0x200) tmp |= 0x80;
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- write3X4(par, CRTOverflow, tmp);
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+ write3X4(par, VGA_CRTC_OVERFLOW, tmp);
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tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
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tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
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if (vtotal & 0x400) tmp |= 0x80;
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if (vtotal & 0x400) tmp |= 0x80;
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@@ -989,11 +968,11 @@ static int tridentfb_set_par(struct fb_info *info)
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tmp = 0x40;
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tmp = 0x40;
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if (vblankstart & 0x200) tmp |= 0x20;
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if (vblankstart & 0x200) tmp |= 0x20;
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//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
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//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
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- write3X4(par, CRTMaxScanLine, tmp);
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+ write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
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- write3X4(par, CRTLineCompare, 0xFF);
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- write3X4(par, CRTPRowScan, 0);
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- write3X4(par, CRTModeControl, 0xC3);
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+ write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
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+ write3X4(par, VGA_CRTC_PRESET_ROW, 0);
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+ write3X4(par, VGA_CRTC_MODE, 0xC3);
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write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
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write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
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@@ -1041,12 +1020,12 @@ static int tridentfb_set_par(struct fb_info *info)
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vclk *= 2;
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vclk *= 2;
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set_vclk(par, vclk);
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set_vclk(par, vclk);
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- write3C4(par, 0, 3);
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- write3C4(par, 1, 1); /* set char clock 8 dots wide */
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+ vga_mm_wseq(par->io_virt, 0, 3);
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+ vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
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/* enable 4 maps because needed in chain4 mode */
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/* enable 4 maps because needed in chain4 mode */
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- write3C4(par, 2, 0x0F);
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- write3C4(par, 3, 0);
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- write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */
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+ vga_mm_wseq(par->io_virt, 2, 0x0F);
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+ vga_mm_wseq(par->io_virt, 3, 0);
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+ vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
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/* divide clock by 2 if 32bpp chain4 mode display and CPU path */
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/* divide clock by 2 if 32bpp chain4 mode display and CPU path */
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write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
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write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
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@@ -1056,7 +1035,7 @@ static int tridentfb_set_par(struct fb_info *info)
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if (par->chip_id == CYBERBLADEXPAi1) {
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if (par->chip_id == CYBERBLADEXPAi1) {
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/* This fixes snow-effect in 32 bpp */
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/* This fixes snow-effect in 32 bpp */
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- write3X4(par, CRTHSyncStart, 0x84);
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+ write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
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}
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}
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/* graphics mode and support 256 color modes */
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/* graphics mode and support 256 color modes */
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@@ -1067,8 +1046,8 @@ static int tridentfb_set_par(struct fb_info *info)
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/* colors */
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/* colors */
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for (tmp = 0; tmp < 0x10; tmp++)
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for (tmp = 0; tmp < 0x10; tmp++)
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writeAttr(par, tmp, tmp);
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writeAttr(par, tmp, tmp);
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- fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
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- t_outb(par, 0x20, 0x3C0); /* enable attr */
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+ fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
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+ t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
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switch (bpp) {
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switch (bpp) {
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case 8:
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case 8:
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@@ -1086,13 +1065,13 @@ static int tridentfb_set_par(struct fb_info *info)
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break;
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break;
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}
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}
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- t_inb(par, 0x3C8);
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- t_inb(par, 0x3C6);
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- t_inb(par, 0x3C6);
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- t_inb(par, 0x3C6);
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- t_inb(par, 0x3C6);
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- t_outb(par, tmp, 0x3C6);
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- t_inb(par, 0x3C8);
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+ t_inb(par, VGA_PEL_IW);
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+ t_inb(par, VGA_PEL_MSK);
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+ t_inb(par, VGA_PEL_MSK);
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+ t_inb(par, VGA_PEL_MSK);
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+ t_inb(par, VGA_PEL_MSK);
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+ t_outb(par, tmp, VGA_PEL_MSK);
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+ t_inb(par, VGA_PEL_IW);
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if (par->flatpanel)
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if (par->flatpanel)
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set_number_of_lines(par, info->var.yres);
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set_number_of_lines(par, info->var.yres);
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@@ -1116,12 +1095,12 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
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return 1;
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return 1;
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if (bpp == 8) {
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if (bpp == 8) {
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- t_outb(par, 0xFF, 0x3C6);
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- t_outb(par, regno, 0x3C8);
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+ t_outb(par, 0xFF, VGA_PEL_MSK);
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+ t_outb(par, regno, VGA_PEL_IW);
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- t_outb(par, red >> 10, 0x3C9);
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- t_outb(par, green >> 10, 0x3C9);
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- t_outb(par, blue >> 10, 0x3C9);
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+ t_outb(par, red >> 10, VGA_PEL_D);
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+ t_outb(par, green >> 10, VGA_PEL_D);
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+ t_outb(par, blue >> 10, VGA_PEL_D);
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} else if (regno < 16) {
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} else if (regno < 16) {
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if (bpp == 16) { /* RGB 565 */
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if (bpp == 16) { /* RGB 565 */
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|
@@ -1232,8 +1211,7 @@ static int __devinit trident_pci_probe(struct pci_dev *dev,
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/* If PCI id is 0x9660 then further detect chip type */
|
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/* If PCI id is 0x9660 then further detect chip type */
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|
|
if (chip_id == TGUI9660) {
|
|
if (chip_id == TGUI9660) {
|
|
- outb(RevisionID, 0x3C4);
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|
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- revision = inb(0x3C5);
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|
|
+ revision = vga_io_rseq(RevisionID);
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|
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|
|
switch (revision) {
|
|
switch (revision) {
|
|
case 0x22:
|
|
case 0x22:
|