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@@ -1,52 +1,52 @@
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-#include <linux/init.h>
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-#include <linux/kernel.h>
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-#include <linux/sched.h>
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-#include <linux/string.h>
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#include <linux/bootmem.h>
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+#include <linux/linkage.h>
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#include <linux/bitops.h>
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+#include <linux/kernel.h>
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#include <linux/module.h>
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-#include <linux/kgdb.h>
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-#include <linux/topology.h>
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+#include <linux/percpu.h>
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+#include <linux/string.h>
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#include <linux/delay.h>
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+#include <linux/sched.h>
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+#include <linux/init.h>
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+#include <linux/kgdb.h>
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#include <linux/smp.h>
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-#include <linux/percpu.h>
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-#include <asm/i387.h>
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-#include <asm/msr.h>
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-#include <asm/io.h>
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-#include <asm/linkage.h>
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+#include <linux/io.h>
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+
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+#include <asm/stackprotector.h>
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#include <asm/mmu_context.h>
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+#include <asm/hypervisor.h>
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+#include <asm/processor.h>
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+#include <asm/sections.h>
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+#include <asm/topology.h>
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+#include <asm/cpumask.h>
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+#include <asm/pgtable.h>
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+#include <asm/atomic.h>
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+#include <asm/proto.h>
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+#include <asm/setup.h>
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+#include <asm/apic.h>
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+#include <asm/desc.h>
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+#include <asm/i387.h>
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#include <asm/mtrr.h>
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+#include <asm/numa.h>
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+#include <asm/asm.h>
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+#include <asm/cpu.h>
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#include <asm/mce.h>
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+#include <asm/msr.h>
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#include <asm/pat.h>
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-#include <asm/asm.h>
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-#include <asm/numa.h>
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#include <asm/smp.h>
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-#include <asm/cpu.h>
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-#include <asm/cpumask.h>
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-#include <asm/apic.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/uv/uv.h>
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#endif
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-#include <asm/pgtable.h>
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-#include <asm/processor.h>
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-#include <asm/desc.h>
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-#include <asm/atomic.h>
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-#include <asm/proto.h>
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-#include <asm/sections.h>
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-#include <asm/setup.h>
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-#include <asm/hypervisor.h>
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-#include <asm/stackprotector.h>
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-
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#include "cpu.h"
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#ifdef CONFIG_X86_64
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/* all of these masks are initialized in setup_cpu_local_masks() */
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-cpumask_var_t cpu_callin_mask;
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-cpumask_var_t cpu_callout_mask;
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cpumask_var_t cpu_initialized_mask;
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+cpumask_var_t cpu_callout_mask;
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+cpumask_var_t cpu_callin_mask;
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/* representing cpus for which sibling maps can be computed */
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cpumask_var_t cpu_sibling_setup_mask;
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@@ -62,15 +62,15 @@ void __init setup_cpu_local_masks(void)
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#else /* CONFIG_X86_32 */
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-cpumask_t cpu_callin_map;
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+cpumask_t cpu_sibling_setup_map;
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cpumask_t cpu_callout_map;
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cpumask_t cpu_initialized;
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-cpumask_t cpu_sibling_setup_map;
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+cpumask_t cpu_callin_map;
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#endif /* CONFIG_X86_32 */
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-static struct cpu_dev *this_cpu __cpuinitdata;
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+static const struct cpu_dev *this_cpu __cpuinitdata;
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DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
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#ifdef CONFIG_X86_64
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@@ -79,48 +79,48 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
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* IRET will check the segment types kkeil 2000/10/28
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* Also sysret mandates a special GDT layout
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*
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- * The TLS descriptors are currently at a different place compared to i386.
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+ * TLS descriptors are currently at a different place compared to i386.
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* Hopefully nobody expects them at a fixed place (Wine?)
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*/
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- [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
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- [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
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- [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
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- [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
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- [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
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- [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
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+ [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
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+ [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
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+ [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
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+ [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
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+ [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
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+ [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
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#else
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- [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
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- [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
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- [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
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- [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
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+ [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
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+ [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
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+ [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
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+ [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
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/*
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* Segments used for calling PnP BIOS have byte granularity.
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* They code segments and data segments have fixed 64k limits,
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* the transfer segment sizes are set at run time.
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*/
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/* 32-bit code */
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- [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
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+ [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
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/* 16-bit code */
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- [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
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+ [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
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/* 16-bit data */
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- [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
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+ [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
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/* 16-bit data */
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- [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
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+ [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
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/* 16-bit data */
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- [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
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+ [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
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/*
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* The APM segments have byte granularity and their bases
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* are set at run time. All have 64k limits.
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*/
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/* 32-bit code */
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- [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
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+ [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
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/* 16-bit code */
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- [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
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+ [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
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/* data */
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- [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
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+ [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
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- [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
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- [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
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+ [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
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+ [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
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GDT_STACK_CANARY_INIT
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#endif
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} };
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@@ -164,16 +164,17 @@ static inline int flag_is_changeable_p(u32 flag)
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* the CPUID. Add "volatile" to not allow gcc to
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* optimize the subsequent calls to this function.
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*/
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- asm volatile ("pushfl\n\t"
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- "pushfl\n\t"
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- "popl %0\n\t"
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- "movl %0,%1\n\t"
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- "xorl %2,%0\n\t"
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- "pushl %0\n\t"
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- "popfl\n\t"
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- "pushfl\n\t"
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- "popl %0\n\t"
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- "popfl\n\t"
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+ asm volatile ("pushfl \n\t"
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+ "pushfl \n\t"
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+ "popl %0 \n\t"
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+ "movl %0, %1 \n\t"
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+ "xorl %2, %0 \n\t"
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+ "pushl %0 \n\t"
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+ "popfl \n\t"
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+ "pushfl \n\t"
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+ "popl %0 \n\t"
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+ "popfl \n\t"
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+
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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@@ -188,18 +189,22 @@ static int __cpuinit have_cpuid_p(void)
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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- if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
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- /* Disable processor serial number */
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- unsigned long lo, hi;
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- rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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- lo |= 0x200000;
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- wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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- printk(KERN_NOTICE "CPU serial number disabled.\n");
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- clear_cpu_cap(c, X86_FEATURE_PN);
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-
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- /* Disabling the serial number may affect the cpuid level */
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- c->cpuid_level = cpuid_eax(0);
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- }
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+ unsigned long lo, hi;
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+
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+ if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
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+ return;
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+
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+ /* Disable processor serial number: */
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+
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+ rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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+ lo |= 0x200000;
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+ wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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+
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+ printk(KERN_NOTICE "CPU serial number disabled.\n");
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+ clear_cpu_cap(c, X86_FEATURE_PN);
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+
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+ /* Disabling the serial number may affect the cpuid level */
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+ c->cpuid_level = cpuid_eax(0);
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}
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static int __init x86_serial_nr_setup(char *s)
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@@ -232,6 +237,7 @@ struct cpuid_dependent_feature {
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u32 feature;
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u32 level;
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};
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+
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static const struct cpuid_dependent_feature __cpuinitconst
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cpuid_dependent_features[] = {
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{ X86_FEATURE_MWAIT, 0x00000005 },
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@@ -243,7 +249,11 @@ cpuid_dependent_features[] = {
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static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
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{
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const struct cpuid_dependent_feature *df;
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+
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for (df = cpuid_dependent_features; df->feature; df++) {
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+
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+ if (!cpu_has(c, df->feature))
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+ continue;
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/*
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* Note: cpuid_level is set to -1 if unavailable, but
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* extended_extended_level is set to 0 if unavailable
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@@ -251,32 +261,32 @@ static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
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* when signed; hence the weird messing around with
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* signs here...
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*/
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- if (cpu_has(c, df->feature) &&
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- ((s32)df->level < 0 ?
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+ if (!((s32)df->level < 0 ?
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(u32)df->level > (u32)c->extended_cpuid_level :
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- (s32)df->level > (s32)c->cpuid_level)) {
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- clear_cpu_cap(c, df->feature);
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- if (warn)
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- printk(KERN_WARNING
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- "CPU: CPU feature %s disabled "
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- "due to lack of CPUID level 0x%x\n",
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- x86_cap_flags[df->feature],
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- df->level);
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- }
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+ (s32)df->level > (s32)c->cpuid_level))
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+ continue;
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+
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+ clear_cpu_cap(c, df->feature);
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+ if (!warn)
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+ continue;
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+
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+ printk(KERN_WARNING
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+ "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
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+ x86_cap_flags[df->feature], df->level);
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}
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}
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/*
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* Naming convention should be: <Name> [(<Codename>)]
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* This table only is used unless init_<vendor>() below doesn't set it;
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- * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
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- *
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+ * in particular, if CPUID levels 0x80000002..4 are supported, this
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+ * isn't used
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*/
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/* Look up CPU names by table lookup. */
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-static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
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+static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
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{
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- struct cpu_model_info *info;
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+ const struct cpu_model_info *info;
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if (c->x86_model >= 16)
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return NULL; /* Range check */
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@@ -307,8 +317,10 @@ void load_percpu_segment(int cpu)
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load_stack_canary_segment();
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}
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-/* Current gdt points %fs at the "master" per-cpu area: after this,
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- * it's on the real one. */
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+/*
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+ * Current gdt points %fs at the "master" per-cpu area: after this,
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+ * it's on the real one.
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+ */
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void switch_to_new_gdt(int cpu)
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{
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struct desc_ptr gdt_descr;
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@@ -321,7 +333,7 @@ void switch_to_new_gdt(int cpu)
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load_percpu_segment(cpu);
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}
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-static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
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+static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
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static void __cpuinit default_init(struct cpuinfo_x86 *c)
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{
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@@ -340,7 +352,7 @@ static void __cpuinit default_init(struct cpuinfo_x86 *c)
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#endif
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}
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-static struct cpu_dev __cpuinitdata default_cpu = {
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+static const struct cpu_dev __cpuinitconst default_cpu = {
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.c_init = default_init,
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.c_vendor = "Unknown",
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.c_x86_vendor = X86_VENDOR_UNKNOWN,
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@@ -354,22 +366,24 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
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if (c->extended_cpuid_level < 0x80000004)
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return;
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- v = (unsigned int *) c->x86_model_id;
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+ v = (unsigned int *)c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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- /* Intel chips right-justify this string for some dumb reason;
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- undo that brain damage */
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+ /*
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+ * Intel chips right-justify this string for some dumb reason;
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+ * undo that brain damage:
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+ */
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p = q = &c->x86_model_id[0];
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while (*p == ' ')
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- p++;
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+ p++;
|
|
|
if (p != q) {
|
|
|
- while (*p)
|
|
|
- *q++ = *p++;
|
|
|
- while (q <= &c->x86_model_id[48])
|
|
|
- *q++ = '\0'; /* Zero-pad the rest */
|
|
|
+ while (*p)
|
|
|
+ *q++ = *p++;
|
|
|
+ while (q <= &c->x86_model_id[48])
|
|
|
+ *q++ = '\0'; /* Zero-pad the rest */
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -438,27 +452,30 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
|
|
|
|
|
|
if (smp_num_siblings == 1) {
|
|
|
printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
|
|
|
- } else if (smp_num_siblings > 1) {
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
|
|
|
- if (smp_num_siblings > nr_cpu_ids) {
|
|
|
- printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
|
|
|
- smp_num_siblings);
|
|
|
- smp_num_siblings = 1;
|
|
|
- return;
|
|
|
- }
|
|
|
+ if (smp_num_siblings <= 1)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ if (smp_num_siblings > nr_cpu_ids) {
|
|
|
+ pr_warning("CPU: Unsupported number of siblings %d",
|
|
|
+ smp_num_siblings);
|
|
|
+ smp_num_siblings = 1;
|
|
|
+ return;
|
|
|
+ }
|
|
|
|
|
|
- index_msb = get_count_order(smp_num_siblings);
|
|
|
- c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
|
|
|
+ index_msb = get_count_order(smp_num_siblings);
|
|
|
+ c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
|
|
|
|
|
|
- smp_num_siblings = smp_num_siblings / c->x86_max_cores;
|
|
|
+ smp_num_siblings = smp_num_siblings / c->x86_max_cores;
|
|
|
|
|
|
- index_msb = get_count_order(smp_num_siblings);
|
|
|
+ index_msb = get_count_order(smp_num_siblings);
|
|
|
|
|
|
- core_bits = get_count_order(c->x86_max_cores);
|
|
|
+ core_bits = get_count_order(c->x86_max_cores);
|
|
|
|
|
|
- c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
|
|
|
- ((1 << core_bits) - 1);
|
|
|
- }
|
|
|
+ c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
|
|
|
+ ((1 << core_bits) - 1);
|
|
|
|
|
|
out:
|
|
|
if ((c->x86_max_cores * smp_num_siblings) > 1) {
|
|
@@ -473,8 +490,8 @@ out:
|
|
|
static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
|
|
|
{
|
|
|
char *v = c->x86_vendor_id;
|
|
|
- int i;
|
|
|
static int printed;
|
|
|
+ int i;
|
|
|
|
|
|
for (i = 0; i < X86_VENDOR_NUM; i++) {
|
|
|
if (!cpu_devs[i])
|
|
@@ -483,6 +500,7 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
|
|
|
if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
|
|
|
(cpu_devs[i]->c_ident[1] &&
|
|
|
!strcmp(v, cpu_devs[i]->c_ident[1]))) {
|
|
|
+
|
|
|
this_cpu = cpu_devs[i];
|
|
|
c->x86_vendor = this_cpu->c_x86_vendor;
|
|
|
return;
|
|
@@ -491,7 +509,9 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
|
|
|
|
|
|
if (!printed) {
|
|
|
printed++;
|
|
|
- printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
|
|
|
+ printk(KERN_ERR
|
|
|
+ "CPU: vendor_id '%s' unknown, using generic init.\n", v);
|
|
|
+
|
|
|
printk(KERN_ERR "CPU: Your system may be unstable.\n");
|
|
|
}
|
|
|
|
|
@@ -511,14 +531,17 @@ void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
|
|
|
/* Intel-defined flags: level 0x00000001 */
|
|
|
if (c->cpuid_level >= 0x00000001) {
|
|
|
u32 junk, tfms, cap0, misc;
|
|
|
+
|
|
|
cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
|
|
|
c->x86 = (tfms >> 8) & 0xf;
|
|
|
c->x86_model = (tfms >> 4) & 0xf;
|
|
|
c->x86_mask = tfms & 0xf;
|
|
|
+
|
|
|
if (c->x86 == 0xf)
|
|
|
c->x86 += (tfms >> 20) & 0xff;
|
|
|
if (c->x86 >= 0x6)
|
|
|
c->x86_model += ((tfms >> 16) & 0xf) << 4;
|
|
|
+
|
|
|
if (cap0 & (1<<19)) {
|
|
|
c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
|
|
|
c->x86_cache_alignment = c->x86_clflush_size;
|
|
@@ -534,6 +557,7 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
|
|
|
/* Intel-defined flags: level 0x00000001 */
|
|
|
if (c->cpuid_level >= 0x00000001) {
|
|
|
u32 capability, excap;
|
|
|
+
|
|
|
cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
|
|
|
c->x86_capability[0] = capability;
|
|
|
c->x86_capability[4] = excap;
|
|
@@ -542,6 +566,7 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
|
|
|
/* AMD-defined flags: level 0x80000001 */
|
|
|
xlvl = cpuid_eax(0x80000000);
|
|
|
c->extended_cpuid_level = xlvl;
|
|
|
+
|
|
|
if ((xlvl & 0xffff0000) == 0x80000000) {
|
|
|
if (xlvl >= 0x80000001) {
|
|
|
c->x86_capability[1] = cpuid_edx(0x80000001);
|
|
@@ -549,13 +574,15 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-#ifdef CONFIG_X86_64
|
|
|
if (c->extended_cpuid_level >= 0x80000008) {
|
|
|
u32 eax = cpuid_eax(0x80000008);
|
|
|
|
|
|
c->x86_virt_bits = (eax >> 8) & 0xff;
|
|
|
c->x86_phys_bits = eax & 0xff;
|
|
|
}
|
|
|
+#ifdef CONFIG_X86_32
|
|
|
+ else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
|
|
|
+ c->x86_phys_bits = 36;
|
|
|
#endif
|
|
|
|
|
|
if (c->extended_cpuid_level >= 0x80000007)
|
|
@@ -602,8 +629,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
|
|
|
{
|
|
|
#ifdef CONFIG_X86_64
|
|
|
c->x86_clflush_size = 64;
|
|
|
+ c->x86_phys_bits = 36;
|
|
|
+ c->x86_virt_bits = 48;
|
|
|
#else
|
|
|
c->x86_clflush_size = 32;
|
|
|
+ c->x86_phys_bits = 32;
|
|
|
+ c->x86_virt_bits = 32;
|
|
|
#endif
|
|
|
c->x86_cache_alignment = c->x86_clflush_size;
|
|
|
|
|
@@ -634,12 +665,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
|
|
|
|
|
|
void __init early_cpu_init(void)
|
|
|
{
|
|
|
- struct cpu_dev **cdev;
|
|
|
+ const struct cpu_dev *const *cdev;
|
|
|
int count = 0;
|
|
|
|
|
|
- printk("KERNEL supported cpus:\n");
|
|
|
+ printk(KERN_INFO "KERNEL supported cpus:\n");
|
|
|
for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
|
|
|
- struct cpu_dev *cpudev = *cdev;
|
|
|
+ const struct cpu_dev *cpudev = *cdev;
|
|
|
unsigned int j;
|
|
|
|
|
|
if (count >= X86_VENDOR_NUM)
|
|
@@ -650,7 +681,7 @@ void __init early_cpu_init(void)
|
|
|
for (j = 0; j < 2; j++) {
|
|
|
if (!cpudev->c_ident[j])
|
|
|
continue;
|
|
|
- printk(" %s %s\n", cpudev->c_vendor,
|
|
|
+ printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
|
|
|
cpudev->c_ident[j]);
|
|
|
}
|
|
|
}
|
|
@@ -726,9 +757,13 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
|
|
|
c->x86_coreid_bits = 0;
|
|
|
#ifdef CONFIG_X86_64
|
|
|
c->x86_clflush_size = 64;
|
|
|
+ c->x86_phys_bits = 36;
|
|
|
+ c->x86_virt_bits = 48;
|
|
|
#else
|
|
|
c->cpuid_level = -1; /* CPUID not detected */
|
|
|
c->x86_clflush_size = 32;
|
|
|
+ c->x86_phys_bits = 32;
|
|
|
+ c->x86_virt_bits = 32;
|
|
|
#endif
|
|
|
c->x86_cache_alignment = c->x86_clflush_size;
|
|
|
memset(&c->x86_capability, 0, sizeof c->x86_capability);
|
|
@@ -759,8 +794,8 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
|
|
|
squash_the_stupid_serial_number(c);
|
|
|
|
|
|
/*
|
|
|
- * The vendor-specific functions might have changed features. Now
|
|
|
- * we do "generic changes."
|
|
|
+ * The vendor-specific functions might have changed features.
|
|
|
+ * Now we do "generic changes."
|
|
|
*/
|
|
|
|
|
|
/* Filter out anything that depends on CPUID levels we don't have */
|
|
@@ -768,7 +803,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
|
|
|
|
|
|
/* If the model name is still unset, do table lookup. */
|
|
|
if (!c->x86_model_id[0]) {
|
|
|
- char *p;
|
|
|
+ const char *p;
|
|
|
p = table_lookup_model(c);
|
|
|
if (p)
|
|
|
strcpy(c->x86_model_id, p);
|
|
@@ -843,11 +878,11 @@ void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
|
|
|
}
|
|
|
|
|
|
struct msr_range {
|
|
|
- unsigned min;
|
|
|
- unsigned max;
|
|
|
+ unsigned min;
|
|
|
+ unsigned max;
|
|
|
};
|
|
|
|
|
|
-static struct msr_range msr_range_array[] __cpuinitdata = {
|
|
|
+static const struct msr_range msr_range_array[] __cpuinitconst = {
|
|
|
{ 0x00000000, 0x00000418},
|
|
|
{ 0xc0000000, 0xc000040b},
|
|
|
{ 0xc0010000, 0xc0010142},
|
|
@@ -856,14 +891,15 @@ static struct msr_range msr_range_array[] __cpuinitdata = {
|
|
|
|
|
|
static void __cpuinit print_cpu_msr(void)
|
|
|
{
|
|
|
+ unsigned index_min, index_max;
|
|
|
unsigned index;
|
|
|
u64 val;
|
|
|
int i;
|
|
|
- unsigned index_min, index_max;
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
|
|
|
index_min = msr_range_array[i].min;
|
|
|
index_max = msr_range_array[i].max;
|
|
|
+
|
|
|
for (index = index_min; index < index_max; index++) {
|
|
|
if (rdmsrl_amd_safe(index, &val))
|
|
|
continue;
|
|
@@ -873,6 +909,7 @@ static void __cpuinit print_cpu_msr(void)
|
|
|
}
|
|
|
|
|
|
static int show_msr __cpuinitdata;
|
|
|
+
|
|
|
static __init int setup_show_msr(char *arg)
|
|
|
{
|
|
|
int num;
|
|
@@ -894,12 +931,14 @@ __setup("noclflush", setup_noclflush);
|
|
|
|
|
|
void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
|
|
{
|
|
|
- char *vendor = NULL;
|
|
|
+ const char *vendor = NULL;
|
|
|
|
|
|
- if (c->x86_vendor < X86_VENDOR_NUM)
|
|
|
+ if (c->x86_vendor < X86_VENDOR_NUM) {
|
|
|
vendor = this_cpu->c_vendor;
|
|
|
- else if (c->cpuid_level >= 0)
|
|
|
- vendor = c->x86_vendor_id;
|
|
|
+ } else {
|
|
|
+ if (c->cpuid_level >= 0)
|
|
|
+ vendor = c->x86_vendor_id;
|
|
|
+ }
|
|
|
|
|
|
if (vendor && !strstr(c->x86_model_id, vendor))
|
|
|
printk(KERN_CONT "%s ", vendor);
|
|
@@ -926,10 +965,12 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
|
|
static __init int setup_disablecpuid(char *arg)
|
|
|
{
|
|
|
int bit;
|
|
|
+
|
|
|
if (get_option(&arg, &bit) && bit < NCAPINTS*32)
|
|
|
setup_clear_cpu_cap(bit);
|
|
|
else
|
|
|
return 0;
|
|
|
+
|
|
|
return 1;
|
|
|
}
|
|
|
__setup("clearcpuid=", setup_disablecpuid);
|
|
@@ -939,6 +980,7 @@ struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
|
|
|
|
|
|
DEFINE_PER_CPU_FIRST(union irq_stack_union,
|
|
|
irq_stack_union) __aligned(PAGE_SIZE);
|
|
|
+
|
|
|
DEFINE_PER_CPU(char *, irq_stack_ptr) =
|
|
|
init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
|
|
|
|
|
@@ -948,12 +990,21 @@ EXPORT_PER_CPU_SYMBOL(kernel_stack);
|
|
|
|
|
|
DEFINE_PER_CPU(unsigned int, irq_count) = -1;
|
|
|
|
|
|
+/*
|
|
|
+ * Special IST stacks which the CPU switches to when it calls
|
|
|
+ * an IST-marked descriptor entry. Up to 7 stacks (hardware
|
|
|
+ * limit), all of them are 4K, except the debug stack which
|
|
|
+ * is 8K.
|
|
|
+ */
|
|
|
+static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
|
|
|
+ [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
|
|
|
+ [DEBUG_STACK - 1] = DEBUG_STKSZ
|
|
|
+};
|
|
|
+
|
|
|
static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
|
|
|
[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
|
|
|
__aligned(PAGE_SIZE);
|
|
|
|
|
|
-extern asmlinkage void ignore_sysret(void);
|
|
|
-
|
|
|
/* May not be marked __init: used by software suspend */
|
|
|
void syscall_init(void)
|
|
|
{
|
|
@@ -983,7 +1034,7 @@ unsigned long kernel_eflags;
|
|
|
*/
|
|
|
DEFINE_PER_CPU(struct orig_ist, orig_ist);
|
|
|
|
|
|
-#else /* x86_64 */
|
|
|
+#else /* CONFIG_X86_64 */
|
|
|
|
|
|
#ifdef CONFIG_CC_STACKPROTECTOR
|
|
|
DEFINE_PER_CPU(unsigned long, stack_canary);
|
|
@@ -995,9 +1046,26 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
|
|
|
memset(regs, 0, sizeof(struct pt_regs));
|
|
|
regs->fs = __KERNEL_PERCPU;
|
|
|
regs->gs = __KERNEL_STACK_CANARY;
|
|
|
+
|
|
|
return regs;
|
|
|
}
|
|
|
-#endif /* x86_64 */
|
|
|
+#endif /* CONFIG_X86_64 */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Clear all 6 debug registers:
|
|
|
+ */
|
|
|
+static void clear_all_debug_regs(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = 0; i < 8; i++) {
|
|
|
+ /* Ignore db4, db5 */
|
|
|
+ if ((i == 4) || (i == 5))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ set_debugreg(0, i);
|
|
|
+ }
|
|
|
+}
|
|
|
|
|
|
/*
|
|
|
* cpu_init() initializes state that is per-CPU. Some data is already
|
|
@@ -1007,15 +1075,20 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
|
|
|
* A lot of state is already set up in PDA init for 64 bit
|
|
|
*/
|
|
|
#ifdef CONFIG_X86_64
|
|
|
+
|
|
|
void __cpuinit cpu_init(void)
|
|
|
{
|
|
|
- int cpu = stack_smp_processor_id();
|
|
|
- struct tss_struct *t = &per_cpu(init_tss, cpu);
|
|
|
- struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
|
|
|
- unsigned long v;
|
|
|
+ struct orig_ist *orig_ist;
|
|
|
struct task_struct *me;
|
|
|
+ struct tss_struct *t;
|
|
|
+ unsigned long v;
|
|
|
+ int cpu;
|
|
|
int i;
|
|
|
|
|
|
+ cpu = stack_smp_processor_id();
|
|
|
+ t = &per_cpu(init_tss, cpu);
|
|
|
+ orig_ist = &per_cpu(orig_ist, cpu);
|
|
|
+
|
|
|
#ifdef CONFIG_NUMA
|
|
|
if (cpu != 0 && percpu_read(node_number) == 0 &&
|
|
|
cpu_to_node(cpu) != NUMA_NO_NODE)
|
|
@@ -1056,19 +1129,17 @@ void __cpuinit cpu_init(void)
|
|
|
* set up and load the per-CPU TSS
|
|
|
*/
|
|
|
if (!orig_ist->ist[0]) {
|
|
|
- static const unsigned int sizes[N_EXCEPTION_STACKS] = {
|
|
|
- [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
|
|
|
- [DEBUG_STACK - 1] = DEBUG_STKSZ
|
|
|
- };
|
|
|
char *estacks = per_cpu(exception_stacks, cpu);
|
|
|
+
|
|
|
for (v = 0; v < N_EXCEPTION_STACKS; v++) {
|
|
|
- estacks += sizes[v];
|
|
|
+ estacks += exception_stack_sizes[v];
|
|
|
orig_ist->ist[v] = t->x86_tss.ist[v] =
|
|
|
(unsigned long)estacks;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
|
|
|
+
|
|
|
/*
|
|
|
* <= is required because the CPU will access up to
|
|
|
* 8 bits beyond the end of the IO permission bitmap.
|
|
@@ -1097,17 +1168,7 @@ void __cpuinit cpu_init(void)
|
|
|
arch_kgdb_ops.correct_hw_break();
|
|
|
else
|
|
|
#endif
|
|
|
- {
|
|
|
- /*
|
|
|
- * Clear all 6 debug registers:
|
|
|
- */
|
|
|
- set_debugreg(0UL, 0);
|
|
|
- set_debugreg(0UL, 1);
|
|
|
- set_debugreg(0UL, 2);
|
|
|
- set_debugreg(0UL, 3);
|
|
|
- set_debugreg(0UL, 6);
|
|
|
- set_debugreg(0UL, 7);
|
|
|
- }
|
|
|
+ clear_all_debug_regs();
|
|
|
|
|
|
fpu_init();
|
|
|
|
|
@@ -1128,7 +1189,8 @@ void __cpuinit cpu_init(void)
|
|
|
|
|
|
if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
|
|
|
printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
|
|
|
- for (;;) local_irq_enable();
|
|
|
+ for (;;)
|
|
|
+ local_irq_enable();
|
|
|
}
|
|
|
|
|
|
printk(KERN_INFO "Initializing CPU#%d\n", cpu);
|
|
@@ -1157,13 +1219,7 @@ void __cpuinit cpu_init(void)
|
|
|
__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
|
|
|
#endif
|
|
|
|
|
|
- /* Clear all 6 debug registers: */
|
|
|
- set_debugreg(0, 0);
|
|
|
- set_debugreg(0, 1);
|
|
|
- set_debugreg(0, 2);
|
|
|
- set_debugreg(0, 3);
|
|
|
- set_debugreg(0, 6);
|
|
|
- set_debugreg(0, 7);
|
|
|
+ clear_all_debug_regs();
|
|
|
|
|
|
/*
|
|
|
* Force FPU initialization:
|
|
@@ -1183,6 +1239,4 @@ void __cpuinit cpu_init(void)
|
|
|
|
|
|
xsave_init();
|
|
|
}
|
|
|
-
|
|
|
-
|
|
|
#endif
|