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@@ -153,6 +153,21 @@ enum armv7_a9_perf_types {
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ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
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};
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+/* ARMv7 Cortex-A5 specific event types */
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+enum armv7_a5_perf_types {
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+ ARMV7_PERFCTR_IRQ_TAKEN = 0x86,
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+ ARMV7_PERFCTR_FIQ_TAKEN = 0x87,
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+
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+ ARMV7_PERFCTR_EXT_MEM_RQST = 0xc0,
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+ ARMV7_PERFCTR_NC_EXT_MEM_RQST = 0xc1,
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+ ARMV7_PERFCTR_PREFETCH_LINEFILL = 0xc2,
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+ ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
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+ ARMV7_PERFCTR_ENTER_READ_ALLOC = 0xc4,
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+ ARMV7_PERFCTR_READ_ALLOC = 0xc5,
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+
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+ ARMV7_PERFCTR_STALL_SB_FULL = 0xc9,
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+};
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+
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/*
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* Cortex-A8 HW events mapping
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*
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@@ -378,6 +393,122 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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},
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};
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+/*
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+ * Cortex-A5 HW events mapping
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+ */
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+static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
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+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
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+ [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
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+ [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
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+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
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+};
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+
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+static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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+ [PERF_COUNT_HW_CACHE_OP_MAX]
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+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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+ [C(L1D)] = {
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+ [C(OP_READ)] = {
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+ [C(RESULT_ACCESS)]
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+ = ARMV7_PERFCTR_DCACHE_ACCESS,
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+ [C(RESULT_MISS)]
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+ = ARMV7_PERFCTR_DCACHE_REFILL,
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+ },
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+ [C(OP_WRITE)] = {
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+ [C(RESULT_ACCESS)]
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+ = ARMV7_PERFCTR_DCACHE_ACCESS,
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+ [C(RESULT_MISS)]
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+ = ARMV7_PERFCTR_DCACHE_REFILL,
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+ },
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+ [C(OP_PREFETCH)] = {
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+ [C(RESULT_ACCESS)]
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+ = ARMV7_PERFCTR_PREFETCH_LINEFILL,
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+ [C(RESULT_MISS)]
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+ = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
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+ },
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+ },
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+ [C(L1I)] = {
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+ [C(OP_READ)] = {
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+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
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+ [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
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+ },
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+ [C(OP_WRITE)] = {
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+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
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+ [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
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+ },
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+ /*
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+ * The prefetch counters don't differentiate between the I
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+ * side and the D side.
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+ */
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+ [C(OP_PREFETCH)] = {
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+ [C(RESULT_ACCESS)]
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+ = ARMV7_PERFCTR_PREFETCH_LINEFILL,
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+ [C(RESULT_MISS)]
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+ = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
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+ },
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+ },
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+ [C(LL)] = {
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+ [C(OP_READ)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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+ },
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+ [C(OP_WRITE)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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+ },
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+ [C(OP_PREFETCH)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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+ },
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+ },
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+ [C(DTLB)] = {
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+ [C(OP_READ)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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+ },
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+ [C(OP_WRITE)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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+ },
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+ [C(OP_PREFETCH)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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+ },
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+ },
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+ [C(ITLB)] = {
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+ [C(OP_READ)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
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+ },
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+ [C(OP_WRITE)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
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+ },
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+ [C(OP_PREFETCH)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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+ },
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+ },
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+ [C(BPU)] = {
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+ [C(OP_READ)] = {
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+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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+ [C(RESULT_MISS)]
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+ = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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+ },
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+ [C(OP_WRITE)] = {
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+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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+ [C(RESULT_MISS)]
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+ = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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+ },
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+ [C(OP_PREFETCH)] = {
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+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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+ },
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+ },
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+};
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+
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/*
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* Perf Events counters
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*/
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@@ -910,6 +1041,16 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void)
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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return &armv7pmu;
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}
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+
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+static const struct arm_pmu *__init armv7_a5_pmu_init(void)
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+{
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+ armv7pmu.id = ARM_PERF_PMU_ID_CA5;
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+ armv7pmu.name = "ARMv7 Cortex-A5";
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+ armv7pmu.cache_map = &armv7_a5_perf_cache_map;
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+ armv7pmu.event_map = &armv7_a5_perf_map;
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+ armv7pmu.num_events = armv7_read_num_pmnc_events();
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+ return &armv7pmu;
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+}
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#else
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static const struct arm_pmu *__init armv7_a8_pmu_init(void)
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{
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@@ -920,4 +1061,9 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void)
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{
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return NULL;
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}
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+
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+static const struct arm_pmu *__init armv7_a5_pmu_init(void)
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+{
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+ return NULL;
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+}
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#endif /* CONFIG_CPU_V7 */
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