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@@ -472,18 +472,17 @@ bool radeon_card_posted(struct radeon_device *rdev)
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return false;
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/* first check CRTCs */
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- if (ASIC_IS_DCE41(rdev)) {
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+ if (ASIC_IS_DCE4(rdev)) {
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reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
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- if (reg & EVERGREEN_CRTC_MASTER_EN)
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- return true;
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- } else if (ASIC_IS_DCE4(rdev)) {
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- reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
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- RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
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- RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
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- RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
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- RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
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- RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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+ if (rdev->num_crtc >= 4) {
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+ reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
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+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
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+ }
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+ if (rdev->num_crtc >= 6) {
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+ reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
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+ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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+ }
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if (reg & EVERGREEN_CRTC_MASTER_EN)
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return true;
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} else if (ASIC_IS_AVIVO(rdev)) {
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