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@@ -61,6 +61,7 @@ static int32_t e1000_id_led_init(struct e1000_hw *hw);
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static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
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static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
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static void e1000_init_rx_addrs(struct e1000_hw *hw);
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+static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
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static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
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static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
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static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
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@@ -715,6 +716,123 @@ e1000_reset_hw(struct e1000_hw *hw)
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return E1000_SUCCESS;
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}
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+/******************************************************************************
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+ *
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+ * Initialize a number of hardware-dependent bits
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+ *
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+ * hw: Struct containing variables accessed by shared code
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+ *
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+ * This function contains hardware limitation workarounds for PCI-E adapters
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+ *
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+ *****************************************************************************/
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+static void
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+e1000_initialize_hardware_bits(struct e1000_hw *hw)
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+{
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+ if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
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+ /* Settings common to all PCI-express silicon */
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+ uint32_t reg_ctrl, reg_ctrl_ext;
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+ uint32_t reg_tarc0, reg_tarc1;
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+ uint32_t reg_tctl;
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+ uint32_t reg_txdctl, reg_txdctl1;
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+
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+ /* link autonegotiation/sync workarounds */
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+ reg_tarc0 = E1000_READ_REG(hw, TARC0);
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+ reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
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+
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+ /* Enable not-done TX descriptor counting */
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+ reg_txdctl = E1000_READ_REG(hw, TXDCTL);
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+ reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
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+ E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
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+ reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
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+ reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
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+ E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
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+
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+ switch (hw->mac_type) {
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+ case e1000_82571:
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+ case e1000_82572:
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+ /* Clear PHY TX compatible mode bits */
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+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
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+ reg_tarc1 &= ~((1 << 30)|(1 << 29));
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+
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+ /* link autonegotiation/sync workarounds */
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+ reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
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+
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+ /* TX ring control fixes */
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+ reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
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+
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+ /* Multiple read bit is reversed polarity */
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+ reg_tctl = E1000_READ_REG(hw, TCTL);
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+ if (reg_tctl & E1000_TCTL_MULR)
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+ reg_tarc1 &= ~(1 << 28);
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+ else
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+ reg_tarc1 |= (1 << 28);
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+
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+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
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+ break;
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+ case e1000_82573:
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+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
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+ reg_ctrl_ext &= ~(1 << 23);
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+ reg_ctrl_ext |= (1 << 22);
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+
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+ /* TX byte count fix */
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+ reg_ctrl = E1000_READ_REG(hw, CTRL);
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+ reg_ctrl &= ~(1 << 29);
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+
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+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
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+ E1000_WRITE_REG(hw, CTRL, reg_ctrl);
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+ break;
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+ case e1000_80003es2lan:
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+ /* improve small packet performace for fiber/serdes */
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+ if ((hw->media_type == e1000_media_type_fiber) ||
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+ (hw->media_type == e1000_media_type_internal_serdes)) {
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+ reg_tarc0 &= ~(1 << 20);
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+ }
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+
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+ /* Multiple read bit is reversed polarity */
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+ reg_tctl = E1000_READ_REG(hw, TCTL);
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+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
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+ if (reg_tctl & E1000_TCTL_MULR)
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+ reg_tarc1 &= ~(1 << 28);
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+ else
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+ reg_tarc1 |= (1 << 28);
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+
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+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
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+ break;
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+ case e1000_ich8lan:
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+ /* Reduce concurrent DMA requests to 3 from 4 */
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+ if ((hw->revision_id < 3) ||
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+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
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+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
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+ reg_tarc0 |= ((1 << 29)|(1 << 28));
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+
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+ reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
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+ reg_ctrl_ext |= (1 << 22);
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+ E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
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+
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+ /* workaround TX hang with TSO=on */
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+ reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
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+
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+ /* Multiple read bit is reversed polarity */
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+ reg_tctl = E1000_READ_REG(hw, TCTL);
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+ reg_tarc1 = E1000_READ_REG(hw, TARC1);
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+ if (reg_tctl & E1000_TCTL_MULR)
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+ reg_tarc1 &= ~(1 << 28);
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+ else
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+ reg_tarc1 |= (1 << 28);
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+
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+ /* workaround TX hang with TSO=on */
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+ reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
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+
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+ E1000_WRITE_REG(hw, TARC1, reg_tarc1);
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ E1000_WRITE_REG(hw, TARC0, reg_tarc0);
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+ }
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+}
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+
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/******************************************************************************
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* Performs basic configuration of the adapter.
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*
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@@ -743,14 +861,13 @@ e1000_init_hw(struct e1000_hw *hw)
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DEBUGFUNC("e1000_init_hw");
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/* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
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- if (hw->mac_type == e1000_ich8lan) {
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- reg_data = E1000_READ_REG(hw, TARC0);
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- reg_data |= 0x30000000;
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- E1000_WRITE_REG(hw, TARC0, reg_data);
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-
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- reg_data = E1000_READ_REG(hw, STATUS);
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- reg_data &= ~0x80000000;
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- E1000_WRITE_REG(hw, STATUS, reg_data);
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+ if ((hw->mac_type == e1000_ich8lan) &&
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+ ((hw->revision_id < 3) ||
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+ ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
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+ (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
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+ reg_data = E1000_READ_REG(hw, STATUS);
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+ reg_data &= ~0x80000000;
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+ E1000_WRITE_REG(hw, STATUS, reg_data);
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}
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/* Initialize Identification LED */
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@@ -763,6 +880,9 @@ e1000_init_hw(struct e1000_hw *hw)
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/* Set the media type and TBI compatibility */
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e1000_set_media_type(hw);
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+ /* Must be called after e1000_set_media_type because media_type is used */
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+ e1000_initialize_hardware_bits(hw);
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+
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/* Disabling VLAN filtering. */
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DEBUGOUT("Initializing the IEEE VLAN\n");
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/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
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@@ -854,17 +974,6 @@ e1000_init_hw(struct e1000_hw *hw)
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if (hw->mac_type > e1000_82544) {
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ctrl = E1000_READ_REG(hw, TXDCTL);
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ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
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- switch (hw->mac_type) {
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- default:
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- break;
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- case e1000_82571:
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- case e1000_82572:
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- case e1000_82573:
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- case e1000_ich8lan:
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- case e1000_80003es2lan:
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- ctrl |= E1000_TXDCTL_COUNT_DESC;
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- break;
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- }
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E1000_WRITE_REG(hw, TXDCTL, ctrl);
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}
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@@ -902,8 +1011,6 @@ e1000_init_hw(struct e1000_hw *hw)
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case e1000_ich8lan:
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ctrl = E1000_READ_REG(hw, TXDCTL1);
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ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
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- if (hw->mac_type >= e1000_82571)
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- ctrl |= E1000_TXDCTL_COUNT_DESC;
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E1000_WRITE_REG(hw, TXDCTL1, ctrl);
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break;
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}
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@@ -1143,11 +1250,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
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if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
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E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
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- /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
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+ /* On adapters with a MAC newer than 82544, SWDP 1 will be
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* set when the optics detect a signal. On older adapters, it will be
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* cleared when there is a signal. This applies to fiber media only.
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- * If we're on serdes media, adjust the output amplitude to value set in
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- * the EEPROM.
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+ * If we're on serdes media, adjust the output amplitude to value
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+ * set in the EEPROM.
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*/
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ctrl = E1000_READ_REG(hw, CTRL);
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if (hw->media_type == e1000_media_type_fiber)
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