To make it consistent with the other i.mx SoCs, let's add the cpus nodes. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
@@ -32,6 +32,16 @@
usb1 = &usbhost1;
};
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
asic: asic-interrupt-controller@68000000 {
compatible = "fsl,imx25-asic", "fsl,avic";
interrupt-controller;
@@ -20,6 +20,16 @@
serial4 = &uart5;
+ compatible = "arm,arm1136";
avic: avic-interrupt-controller@60000000 {
compatible = "fsl,imx31-avic", "fsl,avic";
@@ -35,6 +35,16 @@
spi2 = &cspi;
+ #address-cells = <1>;
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
tzic: tz-interrupt-controller@0fffc000 {
compatible = "fsl,imx53-tzic", "fsl,tzic";