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@@ -30,6 +30,8 @@
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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+ * Copyright 2013 Freescale Semiconductor, Inc.
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+ *
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*/
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/** Includes *******************************************************************
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@@ -50,7 +52,6 @@
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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-#include <linux/of_i2c.h>
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#include <linux/platform_data/i2c-imx.h>
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/** Defines ********************************************************************
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@@ -62,12 +63,22 @@
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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-/* IMX I2C registers */
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+/* IMX I2C registers:
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+ * the I2C register offset is different between SoCs,
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+ * to provid support for all these chips, split the
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+ * register offset into a fixed base address and a
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+ * variable shift value, then the full register offset
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+ * will be calculated by
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+ * reg_off = ( reg_base_addr << reg_shift)
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+ */
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#define IMX_I2C_IADR 0x00 /* i2c slave address */
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-#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
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-#define IMX_I2C_I2CR 0x08 /* i2c control */
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-#define IMX_I2C_I2SR 0x0C /* i2c status */
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-#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
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+#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
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+#define IMX_I2C_I2CR 0x02 /* i2c control */
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+#define IMX_I2C_I2SR 0x03 /* i2c status */
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+#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
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+
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+#define IMX_I2C_REGSHIFT 2
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+#define VF610_I2C_REGSHIFT 0
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/* Bits of IMX I2C registers */
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#define I2SR_RXAK 0x01
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@@ -84,6 +95,19 @@
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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+/* register bits different operating codes definition:
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+ * 1) I2SR: Interrupt flags clear operation differ between SoCs:
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+ * - write zero to clear(w0c) INT flag on i.MX,
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+ * - but write one to clear(w1c) INT flag on Vybrid.
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+ * 2) I2CR: I2C module enable operation also differ between SoCs:
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+ * - set I2CR_IEN bit enable the module on i.MX,
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+ * - but clear I2CR_IEN bit enable the module on Vybrid.
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+ */
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+#define I2SR_CLR_OPCODE_W0C 0x0
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+#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
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+#define I2CR_IEN_OPCODE_0 0x0
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+#define I2CR_IEN_OPCODE_1 I2CR_IEN
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+
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/** Variables ******************************************************************
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*******************************************************************************/
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@@ -95,8 +119,12 @@
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*
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* Duplicated divider values removed from list
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*/
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+struct imx_i2c_clk_pair {
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+ u16 div;
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+ u16 val;
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+};
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-static u16 __initdata i2c_clk_div[50][2] = {
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+static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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@@ -112,9 +140,38 @@ static u16 __initdata i2c_clk_div[50][2] = {
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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+/* Vybrid VF610 clock divider, register value pairs */
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+static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
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+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
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+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
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+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
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+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
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+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
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+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
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+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
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+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
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+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
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+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
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+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
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+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
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+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
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+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
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+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
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+};
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+
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enum imx_i2c_type {
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IMX1_I2C,
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IMX21_I2C,
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+ VF610_I2C,
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+};
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+
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+struct imx_i2c_hwdata {
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+ enum imx_i2c_type devtype;
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+ unsigned regshift;
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+ struct imx_i2c_clk_pair *clk_div;
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+ unsigned ndivs;
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+ unsigned i2sr_clr_opcode;
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+ unsigned i2cr_ien_opcode;
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};
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struct imx_i2c_struct {
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@@ -126,16 +183,46 @@ struct imx_i2c_struct {
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unsigned int disable_delay;
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int stopped;
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unsigned int ifdr; /* IMX_I2C_IFDR */
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- enum imx_i2c_type devtype;
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+ const struct imx_i2c_hwdata *hwdata;
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+};
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+
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+static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
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+ .devtype = IMX1_I2C,
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+ .regshift = IMX_I2C_REGSHIFT,
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+ .clk_div = imx_i2c_clk_div,
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+ .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
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+ .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
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+ .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
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+
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+};
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+
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+static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
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+ .devtype = IMX21_I2C,
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+ .regshift = IMX_I2C_REGSHIFT,
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+ .clk_div = imx_i2c_clk_div,
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+ .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
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+ .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
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+ .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
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+
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+};
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+
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+static struct imx_i2c_hwdata vf610_i2c_hwdata = {
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+ .devtype = VF610_I2C,
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+ .regshift = VF610_I2C_REGSHIFT,
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+ .clk_div = vf610_i2c_clk_div,
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+ .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
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+ .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
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+ .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
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+
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};
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static struct platform_device_id imx_i2c_devtype[] = {
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{
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.name = "imx1-i2c",
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- .driver_data = IMX1_I2C,
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+ .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
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}, {
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.name = "imx21-i2c",
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- .driver_data = IMX21_I2C,
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+ .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
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}, {
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/* sentinel */
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}
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@@ -143,15 +230,28 @@ static struct platform_device_id imx_i2c_devtype[] = {
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MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
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static const struct of_device_id i2c_imx_dt_ids[] = {
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- { .compatible = "fsl,imx1-i2c", .data = &imx_i2c_devtype[IMX1_I2C], },
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- { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], },
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+ { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
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+ { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
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+ { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
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static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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{
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- return i2c_imx->devtype == IMX1_I2C;
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+ return i2c_imx->hwdata->devtype == IMX1_I2C;
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+}
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+
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+static inline void imx_i2c_write_reg(unsigned int val,
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+ struct imx_i2c_struct *i2c_imx, unsigned int reg)
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+{
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+ writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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+}
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+
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+static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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+ unsigned int reg)
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+{
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+ return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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}
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/** Functions for IMX I2C adapter driver ***************************************
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@@ -165,7 +265,7 @@ static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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while (1) {
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- temp = readb(i2c_imx->base + IMX_I2C_I2SR);
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+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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if (for_busy && (temp & I2SR_IBB))
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break;
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if (!for_busy && !(temp & I2SR_IBB))
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@@ -196,7 +296,7 @@ static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
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static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
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{
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- if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
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+ if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
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dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
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return -EIO; /* No ACK */
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}
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@@ -213,25 +313,25 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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clk_prepare_enable(i2c_imx->clk);
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- writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
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+ imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
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/* Enable I2C controller */
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- writeb(0, i2c_imx->base + IMX_I2C_I2SR);
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- writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
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+ imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
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+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
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/* Wait controller to be stable */
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udelay(50);
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/* Start I2C transaction */
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- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp |= I2CR_MSTA;
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- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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result = i2c_imx_bus_busy(i2c_imx, 1);
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if (result)
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return result;
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i2c_imx->stopped = 0;
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temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
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- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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return result;
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}
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@@ -242,9 +342,9 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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if (!i2c_imx->stopped) {
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/* Stop I2C transaction */
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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}
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if (is_imx1_i2c(i2c_imx)) {
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/*
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@@ -260,13 +360,15 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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}
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/* Disable I2C controller */
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- writeb(0, i2c_imx->base + IMX_I2C_I2CR);
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+ temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
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+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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clk_disable_unprepare(i2c_imx->clk);
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}
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static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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unsigned int rate)
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{
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+ struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
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unsigned int i2c_clk_rate;
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unsigned int div;
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int i;
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@@ -274,15 +376,15 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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/* Divider value calculation */
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i2c_clk_rate = clk_get_rate(i2c_imx->clk);
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div = (i2c_clk_rate + rate - 1) / rate;
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- if (div < i2c_clk_div[0][0])
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+ if (div < i2c_clk_div[0].div)
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i = 0;
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- else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
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- i = ARRAY_SIZE(i2c_clk_div) - 1;
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+ else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
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+ i = i2c_imx->hwdata->ndivs - 1;
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else
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- for (i = 0; i2c_clk_div[i][0] < div; i++);
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+ for (i = 0; i2c_clk_div[i].div < div; i++);
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/* Store divider value */
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- i2c_imx->ifdr = i2c_clk_div[i][1];
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+ i2c_imx->ifdr = i2c_clk_div[i].val;
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/*
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* There dummy delay is calculated.
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@@ -290,7 +392,7 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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* This delay is used in I2C bus disable function
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* to fix chip hardware bug.
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*/
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- i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
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+ i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
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+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
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/* dev_dbg() can't be used, because adapter is not yet registered */
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@@ -298,7 +400,7 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
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__func__, i2c_clk_rate, div);
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dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
|
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|
- __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
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|
+ __func__, i2c_clk_div[i].val, i2c_clk_div[i].div);
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|
|
#endif
|
|
|
}
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|
|
|
|
@@ -307,12 +409,13 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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|
struct imx_i2c_struct *i2c_imx = dev_id;
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|
unsigned int temp;
|
|
|
|
|
|
- temp = readb(i2c_imx->base + IMX_I2C_I2SR);
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|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
|
|
if (temp & I2SR_IIF) {
|
|
|
/* save status register */
|
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|
i2c_imx->i2csr = temp;
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|
|
temp &= ~I2SR_IIF;
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|
- writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
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|
+ temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
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+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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wake_up(&i2c_imx->queue);
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|
return IRQ_HANDLED;
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|
}
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@@ -328,7 +431,7 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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|
__func__, msgs->addr << 1);
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|
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|
/* write slave address */
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- writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
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+ imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx);
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|
if (result)
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|
return result;
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|
@@ -342,7 +445,7 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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dev_dbg(&i2c_imx->adapter.dev,
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|
"<%s> write byte: B%d=0x%X\n",
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|
__func__, i, msgs->buf[i]);
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|
- writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
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|
+ imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
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|
result = i2c_imx_trx_complete(i2c_imx);
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|
|
if (result)
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|
return result;
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|
@@ -363,7 +466,7 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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|
__func__, (msgs->addr << 1) | 0x01);
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|
|
|
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|
/* write slave address */
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|
- writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
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|
+ imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
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|
result = i2c_imx_trx_complete(i2c_imx);
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|
if (result)
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|
|
return result;
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|
@@ -374,12 +477,12 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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|
dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
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|
|
|
|
|
/* setup bus to read data */
|
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|
- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
|
|
temp &= ~I2CR_MTX;
|
|
|
if (msgs->len - 1)
|
|
|
temp &= ~I2CR_TXAK;
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|
|
- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
|
|
- readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
|
|
|
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
|
|
+ imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
|
|
|
|
|
@@ -393,19 +496,19 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
|
|
|
controller from generating another clock cycle */
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
"<%s> clear MSTA\n", __func__);
|
|
|
- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
|
|
temp &= ~(I2CR_MSTA | I2CR_MTX);
|
|
|
- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
|
|
i2c_imx_bus_busy(i2c_imx, 0);
|
|
|
i2c_imx->stopped = 1;
|
|
|
} else if (i == (msgs->len - 2)) {
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
"<%s> set TXAK\n", __func__);
|
|
|
- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
|
|
temp |= I2CR_TXAK;
|
|
|
- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
|
|
}
|
|
|
- msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
|
|
|
+ msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
"<%s> read byte: B%d=0x%X\n",
|
|
|
__func__, i, msgs->buf[i]);
|
|
@@ -432,9 +535,9 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
|
|
if (i) {
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
"<%s> repeated start\n", __func__);
|
|
|
- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
|
|
temp |= I2CR_RSTA;
|
|
|
- writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
|
|
result = i2c_imx_bus_busy(i2c_imx, 1);
|
|
|
if (result)
|
|
|
goto fail0;
|
|
@@ -443,13 +546,13 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
|
|
"<%s> transfer message: %d\n", __func__, i);
|
|
|
/* write/read data */
|
|
|
#ifdef CONFIG_I2C_DEBUG_BUS
|
|
|
- temp = readb(i2c_imx->base + IMX_I2C_I2CR);
|
|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
|
|
|
"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
|
|
|
(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
|
|
|
(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
|
|
|
(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
|
|
|
- temp = readb(i2c_imx->base + IMX_I2C_I2SR);
|
|
|
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
|
|
|
"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
|
|
@@ -492,7 +595,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
|
&pdev->dev);
|
|
|
struct imx_i2c_struct *i2c_imx;
|
|
|
struct resource *res;
|
|
|
- struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
|
|
|
+ struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
|
|
void __iomem *base;
|
|
|
int irq, ret;
|
|
|
u32 bitrate;
|
|
@@ -518,8 +621,10 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
|
}
|
|
|
|
|
|
if (of_id)
|
|
|
- pdev->id_entry = of_id->data;
|
|
|
- i2c_imx->devtype = pdev->id_entry->driver_data;
|
|
|
+ i2c_imx->hwdata = of_id->data;
|
|
|
+ else
|
|
|
+ i2c_imx->hwdata = (struct imx_i2c_hwdata *)
|
|
|
+ platform_get_device_id(pdev)->driver_data;
|
|
|
|
|
|
/* Setup i2c_imx driver structure */
|
|
|
strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
|
|
@@ -537,6 +642,11 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
|
return PTR_ERR(i2c_imx->clk);
|
|
|
}
|
|
|
|
|
|
+ ret = clk_prepare_enable(i2c_imx->clk);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&pdev->dev, "can't enable I2C clock\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
/* Request IRQ */
|
|
|
ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
|
|
|
pdev->name, i2c_imx);
|
|
@@ -560,8 +670,9 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
|
i2c_imx_set_clk(i2c_imx, bitrate);
|
|
|
|
|
|
/* Set up chip registers to defaults */
|
|
|
- writeb(0, i2c_imx->base + IMX_I2C_I2CR);
|
|
|
- writeb(0, i2c_imx->base + IMX_I2C_I2SR);
|
|
|
+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
|
|
|
+ i2c_imx, IMX_I2C_I2CR);
|
|
|
+ imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
|
|
|
|
|
|
/* Add I2C adapter */
|
|
|
ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
|
|
@@ -570,10 +681,9 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
- of_i2c_register_devices(&i2c_imx->adapter);
|
|
|
-
|
|
|
/* Set up platform driver data */
|
|
|
platform_set_drvdata(pdev, i2c_imx);
|
|
|
+ clk_disable_unprepare(i2c_imx->clk);
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
|
|
@@ -596,10 +706,10 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
|
|
|
i2c_del_adapter(&i2c_imx->adapter);
|
|
|
|
|
|
/* setup chip registers to defaults */
|
|
|
- writeb(0, i2c_imx->base + IMX_I2C_IADR);
|
|
|
- writeb(0, i2c_imx->base + IMX_I2C_IFDR);
|
|
|
- writeb(0, i2c_imx->base + IMX_I2C_I2CR);
|
|
|
- writeb(0, i2c_imx->base + IMX_I2C_I2SR);
|
|
|
+ imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
|
|
|
+ imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
|
|
|
+ imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
|
|
|
+ imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
|
|
|
|
|
|
return 0;
|
|
|
}
|