cyclon2.c 5.3 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Heiko Schocher, hs@denx.de
  4. * Based on ACE1XK.c
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. */
  25. #include <common.h> /* core U-Boot definitions */
  26. #include <altera.h>
  27. #include <ACEX1K.h> /* ACEX device family */
  28. /* Define FPGA_DEBUG to get debug printf's */
  29. #ifdef FPGA_DEBUG
  30. #define PRINTF(fmt,args...) printf (fmt ,##args)
  31. #else
  32. #define PRINTF(fmt,args...)
  33. #endif
  34. /* Note: The assumption is that we cannot possibly run fast enough to
  35. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  36. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  37. * the board config file to slow things down.
  38. */
  39. #ifndef CONFIG_FPGA_DELAY
  40. #define CONFIG_FPGA_DELAY()
  41. #endif
  42. #ifndef CONFIG_SYS_FPGA_WAIT
  43. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
  44. #endif
  45. static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
  46. static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
  47. /* static int CYC2_ps_info( Altera_desc *desc ); */
  48. /* ------------------------------------------------------------------------- */
  49. /* CYCLON2 Generic Implementation */
  50. int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
  51. {
  52. int ret_val = FPGA_FAIL;
  53. switch (desc->iface) {
  54. case passive_serial:
  55. PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
  56. ret_val = CYC2_ps_load (desc, buf, bsize);
  57. break;
  58. /* Add new interface types here */
  59. default:
  60. printf ("%s: Unsupported interface type, %d\n",
  61. __FUNCTION__, desc->iface);
  62. }
  63. return ret_val;
  64. }
  65. int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
  66. {
  67. int ret_val = FPGA_FAIL;
  68. switch (desc->iface) {
  69. case passive_serial:
  70. PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
  71. ret_val = CYC2_ps_dump (desc, buf, bsize);
  72. break;
  73. /* Add new interface types here */
  74. default:
  75. printf ("%s: Unsupported interface type, %d\n",
  76. __FUNCTION__, desc->iface);
  77. }
  78. return ret_val;
  79. }
  80. int CYC2_info( Altera_desc *desc )
  81. {
  82. return FPGA_SUCCESS;
  83. }
  84. /* ------------------------------------------------------------------------- */
  85. /* CYCLON2 Passive Serial Generic Implementation */
  86. static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
  87. {
  88. int ret_val = FPGA_FAIL; /* assume the worst */
  89. Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
  90. int ret = 0;
  91. PRINTF ("%s: start with interface functions @ 0x%p\n",
  92. __FUNCTION__, fn);
  93. if (fn) {
  94. int cookie = desc->cookie; /* make a local copy */
  95. unsigned long ts; /* timestamp */
  96. PRINTF ("%s: Function Table:\n"
  97. "ptr:\t0x%p\n"
  98. "struct: 0x%p\n"
  99. "config:\t0x%p\n"
  100. "status:\t0x%p\n"
  101. "write:\t0x%p\n"
  102. "done:\t0x%p\n\n",
  103. __FUNCTION__, &fn, fn, fn->config, fn->status,
  104. fn->write, fn->done);
  105. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  106. printf ("Loading FPGA Device %d...", cookie);
  107. #endif
  108. /*
  109. * Run the pre configuration function if there is one.
  110. */
  111. if (*fn->pre) {
  112. (*fn->pre) (cookie);
  113. }
  114. /* Establish the initial state */
  115. (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
  116. udelay(2); /* T_cfg > 2us */
  117. /* Wait for nSTATUS to be asserted */
  118. ts = get_timer (0); /* get current time */
  119. do {
  120. CONFIG_FPGA_DELAY ();
  121. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  122. puts ("** Timeout waiting for STATUS to go high.\n");
  123. (*fn->abort) (cookie);
  124. return FPGA_FAIL;
  125. }
  126. } while (!(*fn->status) (cookie));
  127. /* Get ready for the burn */
  128. CONFIG_FPGA_DELAY ();
  129. ret = (*fn->write) (buf, bsize, TRUE, cookie);
  130. if (ret) {
  131. puts ("** Write failed.\n");
  132. (*fn->abort) (cookie);
  133. return FPGA_FAIL;
  134. }
  135. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  136. puts(" OK? ...");
  137. #endif
  138. CONFIG_FPGA_DELAY ();
  139. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  140. putc (' '); /* terminate the dotted line */
  141. #endif
  142. /*
  143. * Checking FPGA's CONF_DONE signal - correctly booted ?
  144. */
  145. if ( ! (*fn->done) (cookie) ) {
  146. puts ("** Booting failed! CONF_DONE is still deasserted.\n");
  147. (*fn->abort) (cookie);
  148. return (FPGA_FAIL);
  149. }
  150. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  151. puts(" OK\n");
  152. #endif
  153. ret_val = FPGA_SUCCESS;
  154. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  155. if (ret_val == FPGA_SUCCESS) {
  156. puts ("Done.\n");
  157. }
  158. else {
  159. puts ("Fail.\n");
  160. }
  161. #endif
  162. (*fn->post) (cookie);
  163. } else {
  164. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  165. }
  166. return ret_val;
  167. }
  168. static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
  169. {
  170. /* Readback is only available through the Slave Parallel and */
  171. /* boundary-scan interfaces. */
  172. printf ("%s: Passive Serial Dumping is unavailable\n",
  173. __FUNCTION__);
  174. return FPGA_FAIL;
  175. }