openrd_base.h 8.0 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Net Insight <www.netinsight.net>
  4. * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
  5. *
  6. * Based on sheevaplug.h:
  7. * (C) Copyright 2009
  8. * Marvell Semiconductor <www.marvell.com>
  9. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27. * MA 02110-1301 USA
  28. */
  29. #ifndef _CONFIG_OPENRD_BASE_H
  30. #define _CONFIG_OPENRD_BASE_H
  31. /*
  32. * Version number information
  33. */
  34. #define CONFIG_IDENT_STRING "\nOpenRD_base"
  35. /*
  36. * High Level Configuration Options (easy to change)
  37. */
  38. #define CONFIG_MARVELL 1
  39. #define CONFIG_ARM926EJS 1 /* Basic Architecture */
  40. #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
  41. #define CONFIG_KIRKWOOD 1 /* SOC Family Name */
  42. #define CONFIG_KW88F6281 1 /* SOC Name */
  43. #define CONFIG_MACH_OPENRD_BASE /* Machine type */
  44. #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
  45. #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
  46. #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
  47. #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
  48. #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
  49. /*
  50. * CLKs configurations
  51. */
  52. #define CONFIG_SYS_HZ 1000
  53. /*
  54. * NS16550 Configuration
  55. */
  56. #define CONFIG_SYS_NS16550
  57. #define CONFIG_SYS_NS16550_SERIAL
  58. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  59. #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
  60. #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
  61. /*
  62. * Serial Port configuration
  63. * The following definitions let you select what serial you want to use
  64. * for your console driver.
  65. */
  66. #define CONFIG_CONS_INDEX 1 /*Console on UART0 */
  67. #define CONFIG_BAUDRATE 115200
  68. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
  69. 115200,230400, 460800, 921600 }
  70. /* auto boot */
  71. #define CONFIG_BOOTDELAY 3 /* default enable autoboot */
  72. /*
  73. * For booting Linux, the board info and command line data
  74. * have to be in the first 8 MB of memory, since this is
  75. * the maximum mapped by the Linux kernel during initialization.
  76. */
  77. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  78. #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
  79. #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
  80. #define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
  81. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
  82. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
  83. +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
  84. /*
  85. * Commands configuration
  86. */
  87. #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
  88. #include <config_cmd_default.h>
  89. #define CONFIG_CMD_AUTOSCRIPT
  90. #define CONFIG_CMD_DHCP
  91. #define CONFIG_CMD_ENV
  92. #define CONFIG_CMD_MII
  93. #define CONFIG_CMD_NAND
  94. #define CONFIG_CMD_PING
  95. #define CONFIG_CMD_USB
  96. #define CONFIG_CMD_IDE
  97. /*
  98. * NAND configuration
  99. */
  100. #ifdef CONFIG_CMD_NAND
  101. #define CONFIG_NAND_KIRKWOOD
  102. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  103. #define NAND_MAX_CHIPS 1
  104. #define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
  105. #define NAND_ALLOW_ERASE_ALL 1
  106. #endif
  107. /*
  108. * Environment variables configurations
  109. */
  110. #ifdef CONFIG_CMD_NAND
  111. #define CONFIG_ENV_IS_IN_NAND 1
  112. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
  113. #else
  114. #define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
  115. #endif
  116. /*
  117. * max 4k env size is enough, but in case of nand
  118. * it has to be rounded to sector size
  119. */
  120. #define CONFIG_ENV_SIZE 0x20000 /* 128k */
  121. #define CONFIG_ENV_ADDR 0x60000
  122. #define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
  123. /*
  124. * Default environment variables
  125. */
  126. #define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
  127. "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
  128. "${x_bootcmd_usb}; bootm 0x6400000;"
  129. #define MTDIDS_DEFAULT "nand0=nand_mtd"
  130. #define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
  131. "0x400000@0x100000(uImage),"\
  132. "0x1fb00000@0x500000(rootfs)"
  133. #define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
  134. "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
  135. "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
  136. "x_bootcmd_usb=usb start\0" \
  137. "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
  138. "mtdids="MTDIDS_DEFAULT"\0" \
  139. "mtdparts="MTDPARTS_DEFAULT"\0"
  140. /*
  141. * Size of malloc() pool
  142. */
  143. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
  144. /* size in bytes reserved for initial data */
  145. #define CONFIG_SYS_GBL_DATA_SIZE 128
  146. /*
  147. * Other required minimal configurations
  148. */
  149. #define CONFIG_SYS_LONGHELP
  150. #define CONFIG_AUTO_COMPLETE
  151. #define CONFIG_CMDLINE_EDITING
  152. #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
  153. #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
  154. #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
  155. #define CONFIG_NR_DRAM_BANKS 4
  156. #define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
  157. #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
  158. #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
  159. #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
  160. #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
  161. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  162. /*
  163. * Ethernet Driver configuration
  164. */
  165. #ifdef CONFIG_CMD_NET
  166. #define CONFIG_NETCONSOLE /* include NetConsole support */
  167. #define CONFIG_NET_MULTI /* specify more that one ports available */
  168. #define CONFIG_MII /* expose smi ove miiphy interface */
  169. #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
  170. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
  171. #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
  172. #define CONFIG_PHY_BASE_ADR 0x8
  173. #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
  174. #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
  175. #endif /* CONFIG_CMD_NET */
  176. /*
  177. * USB/EHCI
  178. */
  179. #ifdef CONFIG_CMD_USB
  180. #define CONFIG_USB_EHCI /* Enable EHCI USB support */
  181. #define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
  182. #define CONFIG_EHCI_IS_TDI
  183. #define CONFIG_USB_STORAGE
  184. #define CONFIG_DOS_PARTITION
  185. #define CONFIG_ISO_PARTITION
  186. #define CONFIG_SUPPORT_VFAT
  187. #endif /* CONFIG_CMD_USB */
  188. /*
  189. * IDe Support on SATA port0
  190. */
  191. #ifdef CONFIG_CMD_IDE
  192. #define __io
  193. #define CONFIG_CMD_EXT2
  194. #define CONFIG_MVSATA_IDE
  195. #define CONFIG_IDE_PREINIT
  196. #define CONFIG_MVSATA_IDE_USE_PORT1
  197. /* Needs byte-swapping for ATA data register */
  198. #define CONFIG_IDE_SWAP_IO
  199. /* Data, registers and alternate blocks are at the same offset */
  200. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
  201. #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
  202. #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
  203. /* Each 8-bit ATA register is aligned to a 4-bytes address */
  204. #define CONFIG_SYS_ATA_STRIDE 4
  205. /* Controller supports 48-bits LBA addressing */
  206. #define CONFIG_LBA48
  207. /* CONFIG_CMD_IDE requires some #defines for ATA registers */
  208. #define CONFIG_SYS_IDE_MAXBUS 2
  209. #define CONFIG_SYS_IDE_MAXDEVICE 2
  210. /* ATA registers base is at SATA controller base */
  211. #define CONFIG_SYS_ATA_BASE_ADDR KW_SATA_BASE
  212. /* ATA bus 0 is Kirkwood port 0 on openrd */
  213. #define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET
  214. /* ATA bus 1 is Kirkwood port 1 on openrd */
  215. #define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET
  216. #endif /* CONFIG_CMD_IDE */
  217. /*
  218. * File system
  219. */
  220. #define CONFIG_CMD_FAT
  221. #define CONFIG_CMD_UBI
  222. #define CONFIG_CMD_UBIFS
  223. #define CONFIG_RBTREE
  224. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  225. #define CONFIG_MTD_PARTITIONS
  226. #define CONFIG_CMD_MTDPARTS
  227. #define CONFIG_LZO
  228. #endif /* _CONFIG_OPENRD_BASE_H */