sacsng.h 32 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  4. *
  5. * (C) Copyright 2000
  6. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * (C) Copyright 2001
  10. * Advent Networks, Inc. <http://www.adventnetworks.com>
  11. * Jay Monkman <jtm@smoothsmoothie.com>
  12. *
  13. * Configuration settings for the WindRiver SBC8260 board.
  14. * See http://www.windriver.com/products/html/sbc8260.html
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. */
  34. #ifndef __CONFIG_H
  35. #define __CONFIG_H
  36. /* Enable debug prints */
  37. #undef DEBUG /* General debug */
  38. #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
  39. /*****************************************************************************
  40. *
  41. * These settings must match the way _your_ board is set up
  42. *
  43. *****************************************************************************/
  44. /* What is the oscillator's (UX2) frequency in Hz? */
  45. #define CONFIG_8260_CLKIN 66666600
  46. /*-----------------------------------------------------------------------
  47. * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  48. *-----------------------------------------------------------------------
  49. * What should MODCK_H be? It is dependent on the oscillator
  50. * frequency, MODCK[1-3], and desired CPM and core frequencies.
  51. * Here are some example values (all frequencies are in MHz):
  52. *
  53. * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
  54. * ------- ---------- --- --- ---- ----- ----- -----
  55. * 0x1 0x5 33 100 133 Open Close Open
  56. * 0x1 0x6 33 100 166 Open Open Close
  57. * 0x1 0x7 33 100 200 Open Open Open
  58. *
  59. * 0x2 0x2 33 133 133 Close Open Close
  60. * 0x2 0x3 33 133 166 Close Open Open
  61. * 0x2 0x4 33 133 200 Open Close Close
  62. * 0x2 0x5 33 133 233 Open Close Open
  63. * 0x2 0x6 33 133 266 Open Open Close
  64. *
  65. * 0x5 0x5 66 133 133 Open Close Open
  66. * 0x5 0x6 66 133 166 Open Open Close
  67. * 0x5 0x7 66 133 200 Open Open Open
  68. * 0x6 0x0 66 133 233 Close Close Close
  69. * 0x6 0x1 66 133 266 Close Close Open
  70. * 0x6 0x2 66 133 300 Close Open Close
  71. */
  72. #define CFG_SBC_MODCK_H 0x05
  73. /* Define this if you want to boot from 0x00000100. If you don't define
  74. * this, you will need to program the bootloader to 0xfff00000, and
  75. * get the hardware reset config words at 0xfe000000. The simplest
  76. * way to do that is to program the bootloader at both addresses.
  77. * It is suggested that you just let U-Boot live at 0x00000000.
  78. */
  79. #define CFG_SBC_BOOT_LOW 1
  80. /* What should the base address of the main FLASH be and how big is
  81. * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
  82. * The main FLASH is whichever is connected to *CS0.
  83. */
  84. #define CFG_FLASH0_BASE 0x40000000
  85. #define CFG_FLASH0_SIZE 2
  86. /* What should the base address of the secondary FLASH be and how big
  87. * is it (in Mbytes)? The secondary FLASH is whichever is connected
  88. * to *CS6.
  89. */
  90. #define CFG_FLASH1_BASE 0x60000000
  91. #define CFG_FLASH1_SIZE 2
  92. /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  93. */
  94. #define CONFIG_VERY_BIG_RAM 1
  95. /* What should be the base address of SDRAM DIMM and how big is
  96. * it (in Mbytes)? This will normally auto-configure via the SPD.
  97. */
  98. #define CFG_SDRAM0_BASE 0x00000000
  99. #define CFG_SDRAM0_SIZE 64
  100. /*
  101. * Memory map example with 64 MB DIMM:
  102. *
  103. * 0x0000 0000 Exception Vector code, 8k
  104. * :
  105. * 0x0000 1FFF
  106. * 0x0000 2000 Free for Application Use
  107. * :
  108. * :
  109. *
  110. * :
  111. * :
  112. * 0x03F5 FF30 Monitor Stack (Growing downward)
  113. * Monitor Stack Buffer (0x80)
  114. * 0x03F5 FFB0 Board Info Data
  115. * 0x03F6 0000 Malloc Arena
  116. * : CFG_ENV_SECT_SIZE, 16k
  117. * : CFG_MALLOC_LEN, 128k
  118. * 0x03FC 0000 RAM Copy of Monitor Code
  119. * : CFG_MONITOR_LEN, 256k
  120. * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
  121. */
  122. #define CONFIG_POST (CFG_POST_MEMORY | \
  123. CFG_POST_CPU)
  124. /*
  125. * select serial console configuration
  126. *
  127. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  128. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  129. * for SCC).
  130. *
  131. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  132. * defined elsewhere.
  133. */
  134. #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
  135. #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
  136. #undef CONFIG_CONS_NONE /* define if console on neither */
  137. #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
  138. /*
  139. * select ethernet configuration
  140. *
  141. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  142. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  143. * for FCC)
  144. *
  145. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  146. * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  147. * from CONFIG_COMMANDS to remove support for networking.
  148. */
  149. #undef CONFIG_ETHER_ON_SCC
  150. #define CONFIG_ETHER_ON_FCC
  151. #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
  152. #ifdef CONFIG_ETHER_ON_SCC
  153. #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
  154. #endif /* CONFIG_ETHER_ON_SCC */
  155. #ifdef CONFIG_ETHER_ON_FCC
  156. #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
  157. #define CONFIG_MII /* MII PHY management */
  158. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  159. /*
  160. * Port pins used for bit-banged MII communictions (if applicable).
  161. */
  162. #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
  163. #define MDIO_ACTIVE (iop->pdir |= 0x40000000)
  164. #define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
  165. #define MDIO_READ ((iop->pdat & 0x40000000) != 0)
  166. #define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
  167. else iop->pdat &= ~0x40000000
  168. #define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
  169. else iop->pdat &= ~0x80000000
  170. #define MIIDELAY udelay(50)
  171. #endif /* CONFIG_ETHER_ON_FCC */
  172. #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
  173. /*
  174. * - RX clk is CLK11
  175. * - TX clk is CLK12
  176. */
  177. # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
  178. #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  179. /*
  180. * - Rx-CLK is CLK13
  181. * - Tx-CLK is CLK14
  182. * - Select bus for bd/buffers (see 28-13)
  183. * - Enable Full Duplex in FSMR
  184. */
  185. # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  186. # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  187. # define CFG_CPMFCR_RAMTYPE 0
  188. # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  189. #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  190. #define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
  191. /*
  192. * Configure for RAM tests.
  193. */
  194. #undef CFG_DRAM_TEST /* calls other tests in board.c */
  195. /*
  196. * Status LED for power up status feedback.
  197. */
  198. #define CONFIG_STATUS_LED 1 /* Status LED enabled */
  199. #define STATUS_LED_PAR im_ioport.iop_ppara
  200. #define STATUS_LED_DIR im_ioport.iop_pdira
  201. #define STATUS_LED_ODR im_ioport.iop_podra
  202. #define STATUS_LED_DAT im_ioport.iop_pdata
  203. #define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
  204. #define STATUS_LED_PERIOD (CFG_HZ)
  205. #define STATUS_LED_STATE STATUS_LED_OFF
  206. #define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
  207. #define STATUS_LED_PERIOD1 (CFG_HZ)
  208. #define STATUS_LED_STATE1 STATUS_LED_OFF
  209. #define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
  210. #define STATUS_LED_PERIOD2 (CFG_HZ/2)
  211. #define STATUS_LED_STATE2 STATUS_LED_ON
  212. #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
  213. #define STATUS_LED_YELLOW 0
  214. #define STATUS_LED_GREEN 1
  215. #define STATUS_LED_RED 2
  216. #define STATUS_LED_BOOT 1
  217. /*
  218. * select SPI support configuration
  219. */
  220. #define CONFIG_SOFT_SPI /* enable SPI driver */
  221. /*
  222. * Software (bit-bang) SPI driver configuration
  223. */
  224. #ifdef CONFIG_SOFT_SPI
  225. /*
  226. * Software (bit-bang) SPI driver configuration
  227. */
  228. #define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
  229. #define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
  230. #define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
  231. #undef SPI_INIT /* no port initialization needed */
  232. #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
  233. #define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
  234. else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
  235. #define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
  236. else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
  237. #define SPI_DELAY /*udelay(1)*/ /* 1/2 SPI clock duration */
  238. #endif /* CONFIG_SOFT_SPI */
  239. /*
  240. * select I2C support configuration
  241. *
  242. * Supported configurations are {none, software, hardware} drivers.
  243. * If the software driver is chosen, there are some additional
  244. * configuration items that the driver uses to drive the port pins.
  245. */
  246. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  247. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  248. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  249. #define CFG_I2C_SLAVE 0x7F
  250. /*
  251. * Software (bit-bang) I2C driver configuration
  252. */
  253. #ifdef CONFIG_SOFT_I2C
  254. #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
  255. #define I2C_ACTIVE (iop->pdir |= 0x00010000)
  256. #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
  257. #define I2C_READ ((iop->pdat & 0x00010000) != 0)
  258. #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
  259. else iop->pdat &= ~0x00010000
  260. #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
  261. else iop->pdat &= ~0x00020000
  262. #define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
  263. #endif /* CONFIG_SOFT_I2C */
  264. /* Define this to reserve an entire FLASH sector for
  265. * environment variables. Otherwise, the environment will be
  266. * put in the same sector as U-Boot, and changing variables
  267. * will erase U-Boot temporarily
  268. */
  269. #define CFG_ENV_IN_OWN_SECT 1
  270. /* Define this to contain any number of null terminated strings that
  271. * will be part of the default enviroment compiled into the boot image.
  272. */
  273. #define CONFIG_EXTRA_ENV_SETTINGS \
  274. "serverip=192.168.123.201\0" \
  275. "ipaddr=192.168.123.203\0" \
  276. "checkhostname=VR8500\0" \
  277. "reprog="\
  278. "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
  279. "protect off 60000000 6003FFFF; " \
  280. "erase 60000000 6003FFFF; " \
  281. "cp.b 140000 60000000 $(filesize); " \
  282. "protect on 60000000 6003FFFF\0" \
  283. "copyenv="\
  284. "protect off 60040000 6004FFFF; " \
  285. "erase 60040000 6004FFFF; " \
  286. "cp.b 40040000 60040000 10000; " \
  287. "protect on 60040000 6004FFFF\0" \
  288. "copyprog="\
  289. "protect off 60000000 6003FFFF; " \
  290. "erase 60000000 6003FFFF; " \
  291. "cp.b 40000000 60000000 40000; " \
  292. "protect on 60000000 6003FFFF\0" \
  293. "zapenv="\
  294. "protect off 40040000 4004FFFF; " \
  295. "erase 40040000 4004FFFF; " \
  296. "protect on 40040000 4004FFFF\0" \
  297. "zapotherenv="\
  298. "protect off 60040000 6004FFFF; " \
  299. "erase 60040000 6004FFFF; " \
  300. "protect on 60040000 6004FFFF\0" \
  301. "root-on-initrd="\
  302. "setenv bootcmd "\
  303. "version\\;" \
  304. "echo\\;" \
  305. "bootp\\;" \
  306. "setenv bootargs root=/dev/ram0 rw quiet " \
  307. "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
  308. "run boot-hook\\;" \
  309. "bootm\0" \
  310. "root-on-initrd-debug="\
  311. "setenv bootcmd "\
  312. "version\\;" \
  313. "echo\\;" \
  314. "bootp\\;" \
  315. "setenv bootargs root=/dev/ram0 rw debug " \
  316. "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
  317. "run debug-hook\\;" \
  318. "run boot-hook\\;" \
  319. "bootm\0" \
  320. "root-on-nfs="\
  321. "setenv bootcmd "\
  322. "version\\;" \
  323. "echo\\;" \
  324. "bootp\\;" \
  325. "setenv bootargs root=/dev/nfs rw quiet " \
  326. "nfsroot=\\$(serverip):\\$(rootpath) " \
  327. "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
  328. "run boot-hook\\;" \
  329. "bootm\0" \
  330. "root-on-nfs-debug="\
  331. "setenv bootcmd "\
  332. "version\\;" \
  333. "echo\\;" \
  334. "bootp\\;" \
  335. "setenv bootargs root=/dev/nfs rw debug " \
  336. "nfsroot=\\$(serverip):\\$(rootpath) " \
  337. "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
  338. "run debug-hook\\;" \
  339. "run boot-hook\\;" \
  340. "bootm\0" \
  341. "debug-checkout="\
  342. "setenv checkhostname;" \
  343. "setenv ethaddr 00:09:70:00:00:01;" \
  344. "bootp;" \
  345. "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) debug " \
  346. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
  347. "run debug-hook;" \
  348. "run boot-hook;" \
  349. "bootm\0" \
  350. "debug-hook="\
  351. "echo ipaddr $(ipaddr);" \
  352. "echo serverip $(serverip);" \
  353. "echo gatewayip $(gatewayip);" \
  354. "echo netmask $(netmask);" \
  355. "echo hostname $(hostname)\0" \
  356. "ana=run adc ; run dac\0" \
  357. "adc=run adc-12 ; run adc-34\0" \
  358. "adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
  359. "adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
  360. "dac=echo ### DAC ; imd.b 11 81 5\0" \
  361. "boot-hook=run ana\0"
  362. /* What should the console's baud rate be? */
  363. #define CONFIG_BAUDRATE 9600
  364. /* Ethernet MAC address */
  365. #define CONFIG_ETHADDR 00:09:70:00:00:00
  366. /* The default Ethernet MAC address can be overwritten just once */
  367. #ifdef CONFIG_ETHADDR
  368. #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  369. #endif
  370. /*
  371. * Define this to do some miscellaneous board-specific initialization.
  372. */
  373. #define CONFIG_MISC_INIT_R
  374. /* Set to a positive value to delay for running BOOTCOMMAND */
  375. #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
  376. /* Be selective on what keys can delay or stop the autoboot process
  377. * To stop use: " "
  378. */
  379. #define CONFIG_AUTOBOOT_KEYED
  380. #define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
  381. #define CONFIG_AUTOBOOT_STOP_STR " "
  382. #undef CONFIG_AUTOBOOT_DELAY_STR
  383. #define CONFIG_ZERO_BOOTDELAY_CHECK
  384. #define DEBUG_BOOTKEYS 0
  385. /* Define a command string that is automatically executed when no character
  386. * is read on the console interface withing "Boot Delay" after reset.
  387. */
  388. #define CONFIG_BOOT_ROOT_INITRD 0 /* Use ram disk for the root file system */
  389. #define CONFIG_BOOT_ROOT_NFS 1 /* Use a NFS mounted root file system */
  390. #if CONFIG_BOOT_ROOT_INITRD
  391. #define CONFIG_BOOTCOMMAND \
  392. "version;" \
  393. "echo;" \
  394. "bootp;" \
  395. "setenv bootargs root=/dev/ram0 rw quiet " \
  396. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
  397. "run boot-hook;" \
  398. "bootm"
  399. #endif /* CONFIG_BOOT_ROOT_INITRD */
  400. #if CONFIG_BOOT_ROOT_NFS
  401. #define CONFIG_BOOTCOMMAND \
  402. "version;" \
  403. "echo;" \
  404. "bootp;" \
  405. "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) quiet " \
  406. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
  407. "run boot-hook;" \
  408. "bootm"
  409. #endif /* CONFIG_BOOT_ROOT_NFS */
  410. #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
  411. #define CONFIG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
  412. /* Add support for a few extra bootp options like:
  413. * - File size
  414. * - DNS
  415. */
  416. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
  417. CONFIG_BOOTP_BOOTFILESIZE | \
  418. CONFIG_BOOTP_DNS)
  419. /* undef this to save memory */
  420. #define CFG_LONGHELP
  421. /* Monitor Command Prompt */
  422. #define CFG_PROMPT "=> "
  423. #undef CFG_HUSH_PARSER
  424. #ifdef CFG_HUSH_PARSER
  425. #define CFG_PROMPT_HUSH_PS2 "> "
  426. #endif
  427. /* What U-Boot subsytems do you want enabled? */
  428. #ifdef CONFIG_ETHER_ON_FCC
  429. # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
  430. CFG_CMD_ELF | \
  431. CFG_CMD_ASKENV | \
  432. CFG_CMD_ECHO | \
  433. CFG_CMD_I2C | \
  434. CFG_CMD_SPI | \
  435. CFG_CMD_SDRAM | \
  436. CFG_CMD_REGINFO | \
  437. CFG_CMD_IMMAP | \
  438. CFG_CMD_MII )
  439. #else
  440. # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
  441. CFG_CMD_ELF | \
  442. CFG_CMD_ASKENV | \
  443. CFG_CMD_ECHO | \
  444. CFG_CMD_I2C | \
  445. CFG_CMD_SPI | \
  446. CFG_CMD_SDRAM | \
  447. CFG_CMD_REGINFO | \
  448. CFG_CMD_IMMAP )
  449. #endif /* CONFIG_ETHER_ON_FCC */
  450. /* Where do the internal registers live? */
  451. #define CFG_IMMR 0xF0000000
  452. /*****************************************************************************
  453. *
  454. * You should not have to modify any of the following settings
  455. *
  456. *****************************************************************************/
  457. #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
  458. #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
  459. #define CONFIG_SACSng 1 /* munged for the SACSng */
  460. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  461. #include <cmd_confdefs.h>
  462. /*
  463. * Miscellaneous configurable options
  464. */
  465. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  466. # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  467. #else
  468. # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  469. #endif
  470. /* Print Buffer Size */
  471. #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
  472. #define CFG_MAXARGS 32 /* max number of command args */
  473. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  474. #define CFG_LOAD_ADDR 0x400000 /* default load address */
  475. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  476. #define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
  477. /* the exception vector table */
  478. /* to the end of the DRAM */
  479. /* less monitor and malloc area */
  480. #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
  481. #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
  482. + CFG_MALLOC_LEN \
  483. + CFG_ENV_SECT_SIZE \
  484. + CFG_STACK_USAGE )
  485. #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
  486. - CFG_MEM_END_USAGE )
  487. /* valid baudrates */
  488. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  489. /*
  490. * Low Level Configuration Settings
  491. * (address mappings, register initial values, etc.)
  492. * You should know what you are doing if you make changes here.
  493. */
  494. #define CFG_FLASH_BASE CFG_FLASH0_BASE
  495. #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
  496. #define CFG_SDRAM_BASE CFG_SDRAM0_BASE
  497. #define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
  498. /*-----------------------------------------------------------------------
  499. * Hard Reset Configuration Words
  500. */
  501. #if defined(CFG_SBC_BOOT_LOW)
  502. # define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
  503. #else
  504. # define CFG_SBC_HRCW_BOOT_FLAGS (0)
  505. #endif /* defined(CFG_SBC_BOOT_LOW) */
  506. /* get the HRCW ISB field from CFG_IMMR */
  507. #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
  508. ((CFG_IMMR & 0x01000000) >> 7) | \
  509. ((CFG_IMMR & 0x00100000) >> 4) )
  510. #define CFG_HRCW_MASTER ( HRCW_BPS10 | \
  511. HRCW_DPPC11 | \
  512. CFG_SBC_HRCW_IMMR | \
  513. HRCW_MMR00 | \
  514. HRCW_LBPC11 | \
  515. HRCW_APPC10 | \
  516. HRCW_CS10PC00 | \
  517. (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
  518. CFG_SBC_HRCW_BOOT_FLAGS )
  519. /* no slaves */
  520. #define CFG_HRCW_SLAVE1 0
  521. #define CFG_HRCW_SLAVE2 0
  522. #define CFG_HRCW_SLAVE3 0
  523. #define CFG_HRCW_SLAVE4 0
  524. #define CFG_HRCW_SLAVE5 0
  525. #define CFG_HRCW_SLAVE6 0
  526. #define CFG_HRCW_SLAVE7 0
  527. /*-----------------------------------------------------------------------
  528. * Definitions for initial stack pointer and data area (in DPRAM)
  529. */
  530. #define CFG_INIT_RAM_ADDR CFG_IMMR
  531. #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
  532. #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
  533. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  534. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  535. /*-----------------------------------------------------------------------
  536. * Start addresses for the final memory configuration
  537. * (Set up by the startup code)
  538. * Please note that CFG_SDRAM_BASE _must_ start at 0
  539. * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
  540. */
  541. #define CFG_MONITOR_BASE CFG_FLASH0_BASE
  542. #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  543. # define CFG_RAMBOOT
  544. #endif
  545. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  546. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  547. /*
  548. * For booting Linux, the board info and command line data
  549. * have to be in the first 8 MB of memory, since this is
  550. * the maximum mapped by the Linux kernel during initialization.
  551. */
  552. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  553. /*-----------------------------------------------------------------------
  554. * FLASH and environment organization
  555. */
  556. #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
  557. #undef CFG_FLASH_PROTECTION /* use hardware protection */
  558. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  559. #define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
  560. #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
  561. #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
  562. #ifndef CFG_RAMBOOT
  563. # define CFG_ENV_IS_IN_FLASH 1
  564. # ifdef CFG_ENV_IN_OWN_SECT
  565. # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  566. # define CFG_ENV_SECT_SIZE 0x10000
  567. # else
  568. # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
  569. # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  570. # define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
  571. # endif /* CFG_ENV_IN_OWN_SECT */
  572. #else
  573. # define CFG_ENV_IS_IN_NVRAM 1
  574. # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  575. # define CFG_ENV_SIZE 0x200
  576. #endif /* CFG_RAMBOOT */
  577. /*-----------------------------------------------------------------------
  578. * Cache Configuration
  579. */
  580. #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  581. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  582. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  583. #endif
  584. /*-----------------------------------------------------------------------
  585. * HIDx - Hardware Implementation-dependent Registers 2-11
  586. *-----------------------------------------------------------------------
  587. * HID0 also contains cache control - initially enable both caches and
  588. * invalidate contents, then the final state leaves only the instruction
  589. * cache enabled. Note that Power-On and Hard reset invalidate the caches,
  590. * but Soft reset does not.
  591. *
  592. * HID1 has only read-only information - nothing to set.
  593. */
  594. #define CFG_HID0_INIT (HID0_ICE |\
  595. HID0_DCE |\
  596. HID0_ICFI |\
  597. HID0_DCI |\
  598. HID0_IFEM |\
  599. HID0_ABE)
  600. #define CFG_HID0_FINAL (HID0_ICE |\
  601. HID0_IFEM |\
  602. HID0_ABE |\
  603. HID0_EMCP)
  604. #define CFG_HID2 0
  605. /*-----------------------------------------------------------------------
  606. * RMR - Reset Mode Register
  607. *-----------------------------------------------------------------------
  608. */
  609. #define CFG_RMR 0
  610. /*-----------------------------------------------------------------------
  611. * BCR - Bus Configuration 4-25
  612. *-----------------------------------------------------------------------
  613. */
  614. #define CFG_BCR (BCR_ETM)
  615. /*-----------------------------------------------------------------------
  616. * SIUMCR - SIU Module Configuration 4-31
  617. *-----------------------------------------------------------------------
  618. */
  619. #define CFG_SIUMCR (SIUMCR_DPPC11 |\
  620. SIUMCR_L2CPC00 |\
  621. SIUMCR_APPC10 |\
  622. SIUMCR_MMR00)
  623. /*-----------------------------------------------------------------------
  624. * SYPCR - System Protection Control 11-9
  625. * SYPCR can only be written once after reset!
  626. *-----------------------------------------------------------------------
  627. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  628. */
  629. #define CFG_SYPCR (SYPCR_SWTC |\
  630. SYPCR_BMT |\
  631. SYPCR_PBME |\
  632. SYPCR_LBME |\
  633. SYPCR_SWRI |\
  634. SYPCR_SWP)
  635. /*-----------------------------------------------------------------------
  636. * TMCNTSC - Time Counter Status and Control 4-40
  637. *-----------------------------------------------------------------------
  638. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  639. * and enable Time Counter
  640. */
  641. #define CFG_TMCNTSC (TMCNTSC_SEC |\
  642. TMCNTSC_ALR |\
  643. TMCNTSC_TCF |\
  644. TMCNTSC_TCE)
  645. /*-----------------------------------------------------------------------
  646. * PISCR - Periodic Interrupt Status and Control 4-42
  647. *-----------------------------------------------------------------------
  648. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  649. * Periodic timer
  650. */
  651. #define CFG_PISCR (PISCR_PS |\
  652. PISCR_PTF |\
  653. PISCR_PTE)
  654. /*-----------------------------------------------------------------------
  655. * SCCR - System Clock Control 9-8
  656. *-----------------------------------------------------------------------
  657. */
  658. #define CFG_SCCR 0
  659. /*-----------------------------------------------------------------------
  660. * RCCR - RISC Controller Configuration 13-7
  661. *-----------------------------------------------------------------------
  662. */
  663. #define CFG_RCCR 0
  664. /*
  665. * Initialize Memory Controller:
  666. *
  667. * Bank Bus Machine PortSz Device
  668. * ---- --- ------- ------ ------
  669. * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
  670. * 1 60x GPCM -- bit (Unused)
  671. * 2 60x SDRAM 64 bit SDRAM (DIMM)
  672. * 3 60x SDRAM 64 bit SDRAM (DIMM)
  673. * 4 60x GPCM -- bit (Unused)
  674. * 5 60x GPCM -- bit (Unused)
  675. * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
  676. */
  677. /*-----------------------------------------------------------------------
  678. * BR0,BR1 - Base Register
  679. * Ref: Section 10.3.1 on page 10-14
  680. * OR0,OR1 - Option Register
  681. * Ref: Section 10.3.2 on page 10-18
  682. *-----------------------------------------------------------------------
  683. */
  684. /* Bank 0 - Primary FLASH
  685. */
  686. /* BR0 is configured as follows:
  687. *
  688. * - Base address of 0x40000000
  689. * - 16 bit port size
  690. * - Data errors checking is disabled
  691. * - Read and write access
  692. * - GPCM 60x bus
  693. * - Access are handled by the memory controller according to MSEL
  694. * - Not used for atomic operations
  695. * - No data pipelining is done
  696. * - Valid
  697. */
  698. #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
  699. BRx_PS_16 |\
  700. BRx_MS_GPCM_P |\
  701. BRx_V)
  702. /* OR0 is configured as follows:
  703. *
  704. * - 4 MB
  705. * - *BCTL0 is asserted upon access to the current memory bank
  706. * - *CW / *WE are negated a quarter of a clock earlier
  707. * - *CS is output at the same time as the address lines
  708. * - Uses a clock cycle length of 5
  709. * - *PSDVAL is generated internally by the memory controller
  710. * unless *GTA is asserted earlier externally.
  711. * - Relaxed timing is generated by the GPCM for accesses
  712. * initiated to this memory region.
  713. * - One idle clock is inserted between a read access from the
  714. * current bank and the next access.
  715. */
  716. #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
  717. ORxG_CSNT |\
  718. ORxG_ACS_DIV1 |\
  719. ORxG_SCY_5_CLK |\
  720. ORxG_TRLX |\
  721. ORxG_EHTR)
  722. /*-----------------------------------------------------------------------
  723. * BR2,BR3 - Base Register
  724. * Ref: Section 10.3.1 on page 10-14
  725. * OR2,OR3 - Option Register
  726. * Ref: Section 10.3.2 on page 10-16
  727. *-----------------------------------------------------------------------
  728. */
  729. /* Bank 2,3 - SDRAM DIMM
  730. */
  731. /* The BR2 is configured as follows:
  732. *
  733. * - Base address of 0x00000000
  734. * - 64 bit port size (60x bus only)
  735. * - Data errors checking is disabled
  736. * - Read and write access
  737. * - SDRAM 60x bus
  738. * - Access are handled by the memory controller according to MSEL
  739. * - Not used for atomic operations
  740. * - No data pipelining is done
  741. * - Valid
  742. */
  743. #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
  744. BRx_PS_64 |\
  745. BRx_MS_SDRAM_P |\
  746. BRx_V)
  747. #define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
  748. BRx_PS_64 |\
  749. BRx_MS_SDRAM_P |\
  750. BRx_V)
  751. /* With a 64 MB DIMM, the OR2 is configured as follows:
  752. *
  753. * - 64 MB
  754. * - 4 internal banks per device
  755. * - Row start address bit is A8 with PSDMR[PBI] = 0
  756. * - 12 row address lines
  757. * - Back-to-back page mode
  758. * - Internal bank interleaving within save device enabled
  759. */
  760. #if (CFG_SDRAM0_SIZE == 64)
  761. #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
  762. ORxS_BPD_4 |\
  763. ORxS_ROWST_PBI0_A8 |\
  764. ORxS_NUMR_12)
  765. #else
  766. #error "INVALID SDRAM CONFIGURATION"
  767. #endif
  768. /*-----------------------------------------------------------------------
  769. * PSDMR - 60x Bus SDRAM Mode Register
  770. * Ref: Section 10.3.3 on page 10-21
  771. *-----------------------------------------------------------------------
  772. */
  773. /* Address that the DIMM SPD memory lives at.
  774. */
  775. #define SDRAM_SPD_ADDR 0x50
  776. #if (CFG_SDRAM0_SIZE == 64)
  777. /* With a 64 MB DIMM, the PSDMR is configured as follows:
  778. *
  779. * - Bank Based Interleaving,
  780. * - Refresh Enable,
  781. * - Address Multiplexing where A5 is output on A14 pin
  782. * (A6 on A15, and so on),
  783. * - use address pins A14-A16 as bank select,
  784. * - A9 is output on SDA10 during an ACTIVATE command,
  785. * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
  786. * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
  787. * is 3 clocks,
  788. * - earliest timing for READ/WRITE command after ACTIVATE command is
  789. * 2 clocks,
  790. * - earliest timing for PRECHARGE after last data was read is 1 clock,
  791. * - earliest timing for PRECHARGE after last data was written is 1 clock,
  792. * - CAS Latency is 2.
  793. */
  794. #define CFG_PSDMR (PSDMR_RFEN |\
  795. PSDMR_SDAM_A14_IS_A5 |\
  796. PSDMR_BSMA_A14_A16 |\
  797. PSDMR_SDA10_PBI0_A9 |\
  798. PSDMR_RFRC_7_CLK |\
  799. PSDMR_PRETOACT_3W |\
  800. PSDMR_ACTTORW_2W |\
  801. PSDMR_LDOTOPRE_1C |\
  802. PSDMR_WRC_1C |\
  803. PSDMR_CL_2)
  804. #else
  805. #error "INVALID SDRAM CONFIGURATION"
  806. #endif
  807. /*
  808. * Shoot for approximately 1MHz on the prescaler.
  809. */
  810. #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
  811. #define CFG_MPTPR MPTPR_PTP_DIV64
  812. #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
  813. #define CFG_MPTPR MPTPR_PTP_DIV32
  814. #else
  815. #warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
  816. #define CFG_MPTPR MPTPR_PTP_DIV32
  817. #endif
  818. #define CFG_PSRT 14
  819. /*-----------------------------------------------------------------------
  820. * BR6 - Base Register
  821. * Ref: Section 10.3.1 on page 10-14
  822. * OR6 - Option Register
  823. * Ref: Section 10.3.2 on page 10-18
  824. *-----------------------------------------------------------------------
  825. */
  826. /* Bank 6 - Secondary FLASH
  827. *
  828. * The secondary FLASH is connected to *CS6
  829. */
  830. #if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
  831. /* BR6 is configured as follows:
  832. *
  833. * - Base address of 0x60000000
  834. * - 16 bit port size
  835. * - Data errors checking is disabled
  836. * - Read and write access
  837. * - GPCM 60x bus
  838. * - Access are handled by the memory controller according to MSEL
  839. * - Not used for atomic operations
  840. * - No data pipelining is done
  841. * - Valid
  842. */
  843. # define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
  844. BRx_PS_16 |\
  845. BRx_MS_GPCM_P |\
  846. BRx_V)
  847. /* OR6 is configured as follows:
  848. *
  849. * - 2 MB
  850. * - *BCTL0 is asserted upon access to the current memory bank
  851. * - *CW / *WE are negated a quarter of a clock earlier
  852. * - *CS is output at the same time as the address lines
  853. * - Uses a clock cycle length of 5
  854. * - *PSDVAL is generated internally by the memory controller
  855. * unless *GTA is asserted earlier externally.
  856. * - Relaxed timing is generated by the GPCM for accesses
  857. * initiated to this memory region.
  858. * - One idle clock is inserted between a read access from the
  859. * current bank and the next access.
  860. */
  861. # define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
  862. ORxG_CSNT |\
  863. ORxG_ACS_DIV1 |\
  864. ORxG_SCY_5_CLK |\
  865. ORxG_TRLX |\
  866. ORxG_EHTR)
  867. #endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
  868. /*
  869. * Internal Definitions
  870. *
  871. * Boot Flags
  872. */
  873. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  874. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  875. #endif /* __CONFIG_H */