io.c 4.0 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <asm/processor.h>
  26. #include <asm/io.h>
  27. #include <asm/ppc4xx-gpio.h>
  28. #include <miiphy.h>
  29. #include <gdsys_fpga.h>
  30. #define PHYREG_CONTROL 0
  31. #define PHYREG_PAGE_ADDRESS 22
  32. #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
  33. #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
  34. enum {
  35. UNITTYPE_CCD_SWITCH = 1,
  36. };
  37. enum {
  38. HWVER_100 = 0,
  39. HWVER_110 = 1,
  40. HWVER_121 = 2,
  41. HWVER_122 = 3,
  42. };
  43. int configure_gbit_phy(unsigned char addr)
  44. {
  45. unsigned short value;
  46. /* select page 2 */
  47. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  48. PHYREG_PAGE_ADDRESS, 0x0002))
  49. goto err_out;
  50. /* disable SGMII autonegotiation */
  51. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  52. PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
  53. goto err_out;
  54. /* select page 0 */
  55. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  56. PHYREG_PAGE_ADDRESS, 0x0000))
  57. goto err_out;
  58. /* switch from powerdown to normal operation */
  59. if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  60. PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
  61. goto err_out;
  62. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  63. PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
  64. goto err_out;
  65. /* reset phy so settings take effect */
  66. if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  67. PHYREG_CONTROL, 0x9140))
  68. goto err_out;
  69. return 0;
  70. err_out:
  71. printf("Error writing to the PHY addr=%02x\n", addr);
  72. return -1;
  73. }
  74. /*
  75. * Check Board Identity:
  76. */
  77. int checkboard(void)
  78. {
  79. ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  80. char *s = getenv("serial#");
  81. u16 versions = in_le16(&fpga->versions);
  82. u16 fpga_version = in_le16(&fpga->fpga_version);
  83. u16 fpga_features = in_le16(&fpga->fpga_features);
  84. unsigned unit_type;
  85. unsigned hardware_version;
  86. unsigned feature_channels;
  87. unsigned feature_expansion;
  88. unit_type = (versions & 0xf000) >> 12;
  89. hardware_version = versions & 0x000f;
  90. feature_channels = fpga_features & 0x007f;
  91. feature_expansion = fpga_features & (1<<15);
  92. printf("Board: ");
  93. printf("CATCenter Io");
  94. if (s != NULL) {
  95. puts(", serial# ");
  96. puts(s);
  97. }
  98. puts("\n ");
  99. switch (unit_type) {
  100. case UNITTYPE_CCD_SWITCH:
  101. printf("CCD-Switch");
  102. break;
  103. default:
  104. printf("UnitType %d(not supported)", unit_type);
  105. break;
  106. }
  107. switch (hardware_version) {
  108. case HWVER_100:
  109. printf(" HW-Ver 1.00\n");
  110. break;
  111. case HWVER_110:
  112. printf(" HW-Ver 1.10\n");
  113. break;
  114. case HWVER_121:
  115. printf(" HW-Ver 1.21\n");
  116. break;
  117. case HWVER_122:
  118. printf(" HW-Ver 1.22\n");
  119. break;
  120. default:
  121. printf(" HW-Ver %d(not supported)\n",
  122. hardware_version);
  123. break;
  124. }
  125. printf(" FPGA V %d.%02d, features:",
  126. fpga_version / 100, fpga_version % 100);
  127. printf(" %d channel(s)", feature_channels);
  128. printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
  129. return 0;
  130. }
  131. /*
  132. * setup Gbit PHYs
  133. */
  134. int last_stage_init(void)
  135. {
  136. ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  137. unsigned int k;
  138. miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
  139. bb_miiphy_read, bb_miiphy_write);
  140. for (k = 0; k < 32; ++k)
  141. configure_gbit_phy(k);
  142. /* take fpga serdes blocks out of reset */
  143. out_le16(&fpga->quad_serdes_reset, 0);
  144. return 0;
  145. }