dp83848.c 4.0 KB

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  1. /*
  2. * National Semiconductor DP83848 PHY Driver for TI DaVinci
  3. * (TMS320DM644x) based boards.
  4. *
  5. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6. *
  7. * --------------------------------------------------------
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <net.h>
  29. #include <dp83848.h>
  30. #include <asm/arch/emac_defs.h>
  31. #ifdef CONFIG_DRIVER_TI_EMAC
  32. #ifdef CONFIG_CMD_NET
  33. int dp83848_is_phy_connected(int phy_addr)
  34. {
  35. u_int16_t id1, id2;
  36. if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
  37. return(0);
  38. if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
  39. return(0);
  40. if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
  41. return(1);
  42. return(0);
  43. }
  44. int dp83848_get_link_speed(int phy_addr)
  45. {
  46. u_int16_t tmp;
  47. volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
  48. if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
  49. return(0);
  50. if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
  51. return(0);
  52. if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
  53. return(0);
  54. /* Speed doesn't matter, there is no setting for it in EMAC... */
  55. if (tmp & DP83848_SPEED) {
  56. if (tmp & DP83848_DUPLEX) {
  57. /* set DM644x EMAC for Full Duplex */
  58. emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
  59. } else {
  60. /*set DM644x EMAC for Half Duplex */
  61. emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
  62. }
  63. return(1);
  64. } else {
  65. if (tmp & DP83848_DUPLEX) {
  66. /* set DM644x EMAC for Full Duplex */
  67. emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
  68. } else {
  69. /*set DM644x EMAC for Half Duplex */
  70. emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
  71. }
  72. return(1);
  73. }
  74. return(0);
  75. }
  76. int dp83848_init_phy(int phy_addr)
  77. {
  78. int ret = 1;
  79. if (!dp83848_get_link_speed(phy_addr)) {
  80. /* Try another time */
  81. udelay(100000);
  82. ret = dp83848_get_link_speed(phy_addr);
  83. }
  84. /* Disable PHY Interrupts */
  85. davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
  86. return(ret);
  87. }
  88. int dp83848_auto_negotiate(int phy_addr)
  89. {
  90. u_int16_t tmp;
  91. if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
  92. return(0);
  93. /* Restart Auto_negotiation */
  94. tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
  95. tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
  96. davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
  97. /* Set the Auto_negotiation Advertisement Register
  98. * MII advertising for Next page, 100BaseTxFD and HD,
  99. * 10BaseTFD and HD, IEEE 802.3
  100. */
  101. tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
  102. DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
  103. davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
  104. /* Read Control Register */
  105. if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
  106. return(0);
  107. tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
  108. davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
  109. /* Restart Auto_negotiation */
  110. tmp |= DP83848_RESTART_AUTONEG;
  111. davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
  112. /*check AutoNegotiate complete */
  113. udelay(10000);
  114. if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
  115. return(0);
  116. if (!(tmp & DP83848_AUTONEG_COMP))
  117. return(0);
  118. return (dp83848_get_link_speed(phy_addr));
  119. }
  120. #endif /* CONFIG_CMD_NET */
  121. #endif /* CONFIG_DRIVER_ETHER */