mxsfb.c 4.9 KB

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  1. /*
  2. * Freescale i.MX23/i.MX28 LCDIF driver
  3. *
  4. * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #include <common.h>
  22. #include <malloc.h>
  23. #include <video_fb.h>
  24. #include <asm/arch/imx-regs.h>
  25. #include <asm/arch/clock.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/errno.h>
  28. #include <asm/io.h>
  29. #include "videomodes.h"
  30. #define PS2KHZ(ps) (1000000000UL / (ps))
  31. static GraphicDevice panel;
  32. /*
  33. * DENX M28EVK:
  34. * setenv videomode
  35. * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  36. * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  37. */
  38. static void mxs_lcd_init(GraphicDevice *panel,
  39. struct ctfb_res_modes *mode, int bpp)
  40. {
  41. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  42. uint32_t word_len = 0, bus_width = 0;
  43. uint8_t valid_data = 0;
  44. /* Kick in the LCDIF clock */
  45. mxs_set_lcdclk(PS2KHZ(mode->pixclock));
  46. /* Restart the LCDIF block */
  47. mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  48. switch (bpp) {
  49. case 24:
  50. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  51. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  52. valid_data = 0x7;
  53. break;
  54. case 18:
  55. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  56. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  57. valid_data = 0x7;
  58. break;
  59. case 16:
  60. word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
  61. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
  62. valid_data = 0xf;
  63. break;
  64. case 8:
  65. word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
  66. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
  67. valid_data = 0xf;
  68. break;
  69. }
  70. writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
  71. LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
  72. &regs->hw_lcdif_ctrl);
  73. writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
  74. &regs->hw_lcdif_ctrl1);
  75. writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
  76. &regs->hw_lcdif_transfer_count);
  77. writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
  78. LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
  79. LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
  80. mode->vsync_len, &regs->hw_lcdif_vdctrl0);
  81. writel(mode->upper_margin + mode->lower_margin +
  82. mode->vsync_len + mode->yres,
  83. &regs->hw_lcdif_vdctrl1);
  84. writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
  85. (mode->left_margin + mode->right_margin +
  86. mode->hsync_len + mode->xres),
  87. &regs->hw_lcdif_vdctrl2);
  88. writel(((mode->left_margin + mode->hsync_len) <<
  89. LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
  90. (mode->upper_margin + mode->vsync_len),
  91. &regs->hw_lcdif_vdctrl3);
  92. writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
  93. &regs->hw_lcdif_vdctrl4);
  94. writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
  95. writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
  96. /* Flush FIFO first */
  97. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
  98. /* Sync signals ON */
  99. setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
  100. /* FIFO cleared */
  101. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
  102. /* RUN! */
  103. writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
  104. }
  105. void *video_hw_init(void)
  106. {
  107. int bpp = -1;
  108. char *penv;
  109. void *fb;
  110. struct ctfb_res_modes mode;
  111. puts("Video: ");
  112. /* Suck display configuration from "videomode" variable */
  113. penv = getenv("videomode");
  114. if (!penv) {
  115. printf("MXSFB: 'videomode' variable not set!");
  116. return NULL;
  117. }
  118. bpp = video_get_params(&mode, penv);
  119. /* fill in Graphic device struct */
  120. sprintf(panel.modeIdent, "%dx%dx%d",
  121. mode.xres, mode.yres, bpp);
  122. panel.winSizeX = mode.xres;
  123. panel.winSizeY = mode.yres;
  124. panel.plnSizeX = mode.xres;
  125. panel.plnSizeY = mode.yres;
  126. switch (bpp) {
  127. case 24:
  128. case 18:
  129. panel.gdfBytesPP = 4;
  130. panel.gdfIndex = GDF_32BIT_X888RGB;
  131. break;
  132. case 16:
  133. panel.gdfBytesPP = 2;
  134. panel.gdfIndex = GDF_16BIT_565RGB;
  135. break;
  136. case 8:
  137. panel.gdfBytesPP = 1;
  138. panel.gdfIndex = GDF__8BIT_INDEX;
  139. break;
  140. default:
  141. printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
  142. return NULL;
  143. }
  144. panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
  145. /* Allocate framebuffer */
  146. fb = malloc(panel.memSize);
  147. if (!fb) {
  148. printf("MXSFB: Error allocating framebuffer!\n");
  149. return NULL;
  150. }
  151. /* Wipe framebuffer */
  152. memset(fb, 0, panel.memSize);
  153. panel.frameAdrs = (u32)fb;
  154. printf("%s\n", panel.modeIdent);
  155. /* Start framebuffer */
  156. mxs_lcd_init(&panel, &mode, bpp);
  157. return (void *)&panel;
  158. }