vitesse.c 6.6 KB

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  1. /*
  2. * Vitesse PHY drivers
  3. *
  4. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  5. * Author: Andy Fleming
  6. * Add vsc8662 phy support - Priyanka Jain
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <miiphy.h>
  23. /* Cicada Auxiliary Control/Status Register */
  24. #define MIIM_CIS82xx_AUX_CONSTAT 0x1c
  25. #define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004
  26. #define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020
  27. #define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018
  28. #define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010
  29. #define MIIM_CIS82xx_AUXCONSTAT_100 0x0008
  30. /* Cicada Extended Control Register 1 */
  31. #define MIIM_CIS82xx_EXT_CON1 0x17
  32. #define MIIM_CIS8201_EXTCON1_INIT 0x0000
  33. /* Cicada 8204 Extended PHY Control Register 1 */
  34. #define MIIM_CIS8204_EPHY_CON 0x17
  35. #define MIIM_CIS8204_EPHYCON_INIT 0x0006
  36. #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
  37. /* Cicada 8204 Serial LED Control Register */
  38. #define MIIM_CIS8204_SLED_CON 0x1b
  39. #define MIIM_CIS8204_SLEDCON_INIT 0x1115
  40. /* Vitesse VSC8601 Extended PHY Control Register 1 */
  41. #define MIIM_VSC8601_EPHY_CON 0x17
  42. #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
  43. #define MIIM_VSC8601_SKEW_CTRL 0x1c
  44. #define PHY_EXT_PAGE_ACCESS 0x1f
  45. /* CIS8201 */
  46. static int vitesse_config(struct phy_device *phydev)
  47. {
  48. /* Override PHY config settings */
  49. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
  50. MIIM_CIS82xx_AUXCONSTAT_INIT);
  51. /* Set up the interface mode */
  52. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1,
  53. MIIM_CIS8201_EXTCON1_INIT);
  54. genphy_config_aneg(phydev);
  55. return 0;
  56. }
  57. static int vitesse_parse_status(struct phy_device *phydev)
  58. {
  59. int speed;
  60. int mii_reg;
  61. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT);
  62. if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX)
  63. phydev->duplex = DUPLEX_FULL;
  64. else
  65. phydev->duplex = DUPLEX_HALF;
  66. speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED;
  67. switch (speed) {
  68. case MIIM_CIS82xx_AUXCONSTAT_GBIT:
  69. phydev->speed = SPEED_1000;
  70. break;
  71. case MIIM_CIS82xx_AUXCONSTAT_100:
  72. phydev->speed = SPEED_100;
  73. break;
  74. default:
  75. phydev->speed = SPEED_10;
  76. break;
  77. }
  78. return 0;
  79. }
  80. static int vitesse_startup(struct phy_device *phydev)
  81. {
  82. genphy_update_link(phydev);
  83. vitesse_parse_status(phydev);
  84. return 0;
  85. }
  86. static int cis8204_config(struct phy_device *phydev)
  87. {
  88. /* Override PHY config settings */
  89. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
  90. MIIM_CIS82xx_AUXCONSTAT_INIT);
  91. genphy_config_aneg(phydev);
  92. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  93. (phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  94. (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
  95. (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
  96. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
  97. MIIM_CIS8204_EPHYCON_INIT |
  98. MIIM_CIS8204_EPHYCON_RGMII);
  99. else
  100. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
  101. MIIM_CIS8204_EPHYCON_INIT);
  102. return 0;
  103. }
  104. /* Vitesse VSC8601 */
  105. int vsc8601_config(struct phy_device *phydev)
  106. {
  107. /* Configure some basic stuff */
  108. #ifdef CONFIG_SYS_VSC8601_SKEWFIX
  109. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
  110. MIIM_VSC8601_EPHY_CON_INIT_SKEW);
  111. #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
  112. phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
  113. #define VSC8101_SKEW \
  114. ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
  115. | (CONFIG_SYS_VSC8601_SKEW_RX << 12))
  116. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
  117. VSC8101_SKEW);
  118. phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
  119. #endif
  120. #endif
  121. genphy_config_aneg(phydev);
  122. return 0;
  123. }
  124. static struct phy_driver VSC8211_driver = {
  125. .name = "Vitesse VSC8211",
  126. .uid = 0xfc4b0,
  127. .mask = 0xffff0,
  128. .features = PHY_GBIT_FEATURES,
  129. .config = &vitesse_config,
  130. .startup = &vitesse_startup,
  131. .shutdown = &genphy_shutdown,
  132. };
  133. static struct phy_driver VSC8221_driver = {
  134. .name = "Vitesse VSC8221",
  135. .uid = 0xfc550,
  136. .mask = 0xffff0,
  137. .features = PHY_GBIT_FEATURES,
  138. .config = &genphy_config_aneg,
  139. .startup = &vitesse_startup,
  140. .shutdown = &genphy_shutdown,
  141. };
  142. static struct phy_driver VSC8244_driver = {
  143. .name = "Vitesse VSC8244",
  144. .uid = 0xfc6c0,
  145. .mask = 0xffff0,
  146. .features = PHY_GBIT_FEATURES,
  147. .config = &genphy_config_aneg,
  148. .startup = &vitesse_startup,
  149. .shutdown = &genphy_shutdown,
  150. };
  151. static struct phy_driver VSC8234_driver = {
  152. .name = "Vitesse VSC8234",
  153. .uid = 0xfc620,
  154. .mask = 0xffff0,
  155. .features = PHY_GBIT_FEATURES,
  156. .config = &genphy_config_aneg,
  157. .startup = &vitesse_startup,
  158. .shutdown = &genphy_shutdown,
  159. };
  160. static struct phy_driver VSC8601_driver = {
  161. .name = "Vitesse VSC8601",
  162. .uid = 0x70420,
  163. .mask = 0xffff0,
  164. .features = PHY_GBIT_FEATURES,
  165. .config = &vsc8601_config,
  166. .startup = &vitesse_startup,
  167. .shutdown = &genphy_shutdown,
  168. };
  169. static struct phy_driver VSC8641_driver = {
  170. .name = "Vitesse VSC8641",
  171. .uid = 0x70430,
  172. .mask = 0xffff0,
  173. .features = PHY_GBIT_FEATURES,
  174. .config = &genphy_config_aneg,
  175. .startup = &vitesse_startup,
  176. .shutdown = &genphy_shutdown,
  177. };
  178. static struct phy_driver VSC8662_driver = {
  179. .name = "Vitesse VSC8662",
  180. .uid = 0x70660,
  181. .mask = 0xffff0,
  182. .features = PHY_GBIT_FEATURES,
  183. .config = &genphy_config_aneg,
  184. .startup = &vitesse_startup,
  185. .shutdown = &genphy_shutdown,
  186. };
  187. /* Vitesse bought Cicada, so we'll put these here */
  188. static struct phy_driver cis8201_driver = {
  189. .name = "CIS8201",
  190. .uid = 0xfc410,
  191. .mask = 0xffff0,
  192. .features = PHY_GBIT_FEATURES,
  193. .config = &vitesse_config,
  194. .startup = &vitesse_startup,
  195. .shutdown = &genphy_shutdown,
  196. };
  197. static struct phy_driver cis8204_driver = {
  198. .name = "Cicada Cis8204",
  199. .uid = 0xfc440,
  200. .mask = 0xffff0,
  201. .features = PHY_GBIT_FEATURES,
  202. .config = &cis8204_config,
  203. .startup = &vitesse_startup,
  204. .shutdown = &genphy_shutdown,
  205. };
  206. int phy_vitesse_init(void)
  207. {
  208. phy_register(&VSC8641_driver);
  209. phy_register(&VSC8601_driver);
  210. phy_register(&VSC8234_driver);
  211. phy_register(&VSC8244_driver);
  212. phy_register(&VSC8211_driver);
  213. phy_register(&VSC8221_driver);
  214. phy_register(&VSC8662_driver);
  215. phy_register(&cis8201_driver);
  216. phy_register(&cis8204_driver);
  217. return 0;
  218. }