icecube.c 8.0 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <mpc5xxx.h>
  28. #include <pci.h>
  29. #if defined(CONFIG_LITE5200B)
  30. #include "mt46v32m16.h"
  31. #else
  32. # if defined(CONFIG_MPC5200_DDR)
  33. # include "mt46v16m16-75.h"
  34. # else
  35. #include "mt48lc16m16a2-75.h"
  36. # endif
  37. #endif
  38. #ifndef CFG_RAMBOOT
  39. static void sdram_start (int hi_addr)
  40. {
  41. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  42. /* unlock mode register */
  43. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  44. __asm__ volatile ("sync");
  45. /* precharge all banks */
  46. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  47. __asm__ volatile ("sync");
  48. #if SDRAM_DDR
  49. /* set mode register: extended mode */
  50. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  51. __asm__ volatile ("sync");
  52. /* set mode register: reset DLL */
  53. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  54. __asm__ volatile ("sync");
  55. #endif
  56. /* precharge all banks */
  57. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  58. __asm__ volatile ("sync");
  59. /* auto refresh */
  60. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  61. __asm__ volatile ("sync");
  62. /* set mode register */
  63. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  64. __asm__ volatile ("sync");
  65. /* normal operation */
  66. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  67. __asm__ volatile ("sync");
  68. }
  69. #endif
  70. /*
  71. * ATTENTION: Although partially referenced initdram does NOT make real use
  72. * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  73. * is something else than 0x00000000.
  74. */
  75. #if defined(CONFIG_MPC5200)
  76. long int initdram (int board_type)
  77. {
  78. ulong dramsize = 0;
  79. ulong dramsize2 = 0;
  80. #ifndef CFG_RAMBOOT
  81. ulong test1, test2;
  82. /* setup SDRAM chip selects */
  83. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  84. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  85. __asm__ volatile ("sync");
  86. /* setup config registers */
  87. *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  88. *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  89. __asm__ volatile ("sync");
  90. #if SDRAM_DDR
  91. /* set tap delay */
  92. *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
  93. __asm__ volatile ("sync");
  94. #endif
  95. /* find RAM size using SDRAM CS0 only */
  96. sdram_start(0);
  97. test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  98. sdram_start(1);
  99. test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  100. if (test1 > test2) {
  101. sdram_start(0);
  102. dramsize = test1;
  103. } else {
  104. dramsize = test2;
  105. }
  106. /* memory smaller than 1MB is impossible */
  107. if (dramsize < (1 << 20)) {
  108. dramsize = 0;
  109. }
  110. /* set SDRAM CS0 size according to the amount of RAM found */
  111. if (dramsize > 0) {
  112. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
  113. } else {
  114. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
  115. }
  116. /* let SDRAM CS1 start right after CS0 */
  117. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
  118. /* find RAM size using SDRAM CS1 only */
  119. if (!dramsize)
  120. sdram_start(0);
  121. test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
  122. if (!dramsize) {
  123. sdram_start(1);
  124. test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
  125. }
  126. if (test1 > test2) {
  127. sdram_start(0);
  128. dramsize2 = test1;
  129. } else {
  130. dramsize2 = test2;
  131. }
  132. /* memory smaller than 1MB is impossible */
  133. if (dramsize2 < (1 << 20)) {
  134. dramsize2 = 0;
  135. }
  136. /* set SDRAM CS1 size according to the amount of RAM found */
  137. if (dramsize2 > 0) {
  138. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
  139. | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
  140. } else {
  141. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
  142. }
  143. #else /* CFG_RAMBOOT */
  144. /* retrieve size of memory connected to SDRAM CS0 */
  145. dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
  146. if (dramsize >= 0x13) {
  147. dramsize = (1 << (dramsize - 0x13)) << 20;
  148. } else {
  149. dramsize = 0;
  150. }
  151. /* retrieve size of memory connected to SDRAM CS1 */
  152. dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
  153. if (dramsize2 >= 0x13) {
  154. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  155. } else {
  156. dramsize2 = 0;
  157. }
  158. #endif /* CFG_RAMBOOT */
  159. return dramsize + dramsize2;
  160. }
  161. #elif defined(CONFIG_MGT5100)
  162. long int initdram (int board_type)
  163. {
  164. ulong dramsize = 0;
  165. #ifndef CFG_RAMBOOT
  166. ulong test1, test2;
  167. /* setup and enable SDRAM chip selects */
  168. *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
  169. *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
  170. *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
  171. __asm__ volatile ("sync");
  172. /* setup config registers */
  173. *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  174. *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  175. /* address select register */
  176. *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
  177. __asm__ volatile ("sync");
  178. /* find RAM size */
  179. sdram_start(0);
  180. test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  181. sdram_start(1);
  182. test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  183. if (test1 > test2) {
  184. sdram_start(0);
  185. dramsize = test1;
  186. } else {
  187. dramsize = test2;
  188. }
  189. /* set SDRAM end address according to size */
  190. *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
  191. #else /* CFG_RAMBOOT */
  192. /* Retrieve amount of SDRAM available */
  193. dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
  194. #endif /* CFG_RAMBOOT */
  195. return dramsize;
  196. }
  197. #else
  198. #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
  199. #endif
  200. int checkboard (void)
  201. {
  202. #if defined (CONFIG_LITE5200B)
  203. puts ("Board: Freescale Lite5200B\n");
  204. #elif defined(CONFIG_MPC5200)
  205. puts ("Board: Motorola MPC5200 (IceCube)\n");
  206. #elif defined(CONFIG_MGT5100)
  207. puts ("Board: Motorola MGT5100 (IceCube)\n");
  208. #endif
  209. return 0;
  210. }
  211. void flash_preinit(void)
  212. {
  213. /*
  214. * Now, when we are in RAM, enable flash write
  215. * access for detection process.
  216. * Note that CS_BOOT cannot be cleared when
  217. * executing in flash.
  218. */
  219. #if defined(CONFIG_MGT5100)
  220. *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
  221. *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
  222. #endif
  223. *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
  224. }
  225. void flash_afterinit(ulong size)
  226. {
  227. if (size == 0x800000) { /* adjust mapping */
  228. *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
  229. START_REG(CFG_BOOTCS_START | size);
  230. *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
  231. STOP_REG(CFG_BOOTCS_START | size, size);
  232. }
  233. }
  234. #ifdef CONFIG_PCI
  235. static struct pci_controller hose;
  236. extern void pci_mpc5xxx_init(struct pci_controller *);
  237. void pci_init_board(void)
  238. {
  239. pci_mpc5xxx_init(&hose);
  240. }
  241. #endif
  242. #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
  243. #define GPIO_PSC1_4 0x01000000UL
  244. void init_ide_reset (void)
  245. {
  246. debug ("init_ide_reset\n");
  247. /* Configure PSC1_4 as GPIO output for ATA reset */
  248. *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
  249. *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
  250. /* Deassert reset */
  251. *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
  252. }
  253. void ide_set_reset (int idereset)
  254. {
  255. debug ("ide_reset(%d)\n", idereset);
  256. if (idereset) {
  257. *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
  258. /* Make a delay. MPC5200 spec says 25 usec min */
  259. udelay(500000);
  260. } else {
  261. *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
  262. }
  263. }
  264. #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */