ddr.c 2.0 KB

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  1. /*
  2. * Copyright 2008 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <asm/fsl_ddr_sdram.h>
  11. #include <asm/fsl_ddr_dimm_params.h>
  12. static void
  13. get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  14. {
  15. i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  16. /* We use soldered memory, but use an SPD EEPROM to describe it.
  17. * The SPD has an unspecified dimm type, but the DDR2 initialization
  18. * code requires a specific type to be specified. This sets the type
  19. * as a standard unregistered SO-DIMM. */
  20. if (spd->dimm_type == 0) {
  21. spd->dimm_type = 0x4;
  22. ((uchar *)spd)[63] += 0x4;
  23. }
  24. }
  25. unsigned int fsl_ddr_get_mem_data_rate(void)
  26. {
  27. return get_ddr_freq(0);
  28. }
  29. void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
  30. unsigned int ctrl_num)
  31. {
  32. unsigned int i;
  33. if (ctrl_num) {
  34. printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
  35. return;
  36. }
  37. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
  38. get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
  39. }
  40. void fsl_ddr_board_options(memctl_options_t *popts,
  41. dimm_params_t *pdimm,
  42. unsigned int ctrl_num)
  43. {
  44. /*
  45. * Factors to consider for clock adjust:
  46. * - number of chips on bus
  47. * - position of slot
  48. * - DDR1 vs. DDR2?
  49. * - ???
  50. *
  51. * This needs to be determined on a board-by-board basis.
  52. * 0110 3/4 cycle late
  53. * 0111 7/8 cycle late
  54. */
  55. popts->clk_adjust = 7;
  56. /*
  57. * Factors to consider for CPO:
  58. * - frequency
  59. * - ddr1 vs. ddr2
  60. */
  61. popts->cpo_override = 9;
  62. /*
  63. * Factors to consider for write data delay:
  64. * - number of DIMMs
  65. *
  66. * 1 = 1/4 clock delay
  67. * 2 = 1/2 clock delay
  68. * 3 = 3/4 clock delay
  69. * 4 = 1 clock delay
  70. * 5 = 5/4 clock delay
  71. * 6 = 3/2 clock delay
  72. */
  73. popts->write_data_delay = 3;
  74. /*
  75. * Factors to consider for half-strength driver enable:
  76. * - number of DIMMs installed
  77. */
  78. popts->half_strength_driver_enable = 0;
  79. }