fsl_85xx_ddr.c 2.2 KB

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  1. /*
  2. * Copyright 2008 Extreme Engineering Solutions, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/fsl_ddr_sdram.h>
  24. #include <asm/mmu.h>
  25. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  26. extern void ddr_enable_ecc(unsigned int dram_size);
  27. #endif
  28. phys_size_t initdram(int board_type)
  29. {
  30. phys_size_t dram_size = fsl_ddr_sdram();
  31. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  32. dram_size *= 0x100000;
  33. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  34. /* Initialize and enable DDR ECC */
  35. ddr_enable_ecc(dram_size);
  36. #endif
  37. return dram_size;
  38. }
  39. #if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
  40. void board_add_ram_info(int use_default)
  41. {
  42. #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
  43. volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
  44. #endif
  45. puts(" (");
  46. #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
  47. /* Print interleaving information */
  48. if (ddr1->cs0_config & 0x20000000) {
  49. switch ((ddr1->cs0_config >> 24) & 0xf) {
  50. case 0:
  51. puts("cache line");
  52. break;
  53. case 1:
  54. puts("page");
  55. break;
  56. case 2:
  57. puts("bank");
  58. break;
  59. case 3:
  60. puts("super-bank");
  61. break;
  62. default:
  63. puts("invalid");
  64. break;
  65. }
  66. } else {
  67. puts("no");
  68. }
  69. puts(" interleaving");
  70. #endif
  71. #if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
  72. puts(", ");
  73. #endif
  74. #if defined(CONFIG_DDR_ECC)
  75. puts("ECC enabled");
  76. #endif
  77. puts(")");
  78. }
  79. #endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */