fsl_pci_init.c 9.0 KB

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  1. /*
  2. * Copyright 2007 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16. * MA 02111-1307 USA
  17. */
  18. #include <common.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /*
  21. * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  22. *
  23. * Initialize controller and call the common driver/pci pci_hose_scan to
  24. * scan for bridges and devices.
  25. *
  26. * Hose fields which need to be pre-initialized by board specific code:
  27. * regions[]
  28. * first_busno
  29. *
  30. * Fields updated:
  31. * last_busno
  32. */
  33. #include <pci.h>
  34. #include <asm/immap_fsl_pci.h>
  35. void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  36. pci_dev_t dev, int sub_bus);
  37. void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  38. pci_dev_t dev, int sub_bus);
  39. void pciauto_config_init(struct pci_controller *hose);
  40. #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  41. #define CONFIG_SYS_PCI_MEMORY_BUS 0
  42. #endif
  43. #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  44. #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  45. #endif
  46. #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  47. #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  48. #endif
  49. int fsl_pci_setup_inbound_windows(struct pci_region *r)
  50. {
  51. struct pci_region *rgn_base = r;
  52. u64 sz = min((u64)gd->ram_size, 1ull << 32);
  53. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  54. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  55. pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
  56. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  57. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  58. pci_set_region(r++, bus_start, phys_start, pci_sz,
  59. PCI_REGION_MEM | PCI_REGION_MEMORY | \
  60. PCI_REGION_PREFETCH);
  61. sz -= pci_sz;
  62. bus_start += pci_sz;
  63. phys_start += pci_sz;
  64. pci_sz = 1ull << __ilog2_u64(sz);
  65. if (sz) {
  66. debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
  67. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  68. pci_set_region(r++, bus_start, phys_start, pci_sz,
  69. PCI_REGION_MEM | PCI_REGION_MEMORY | \
  70. PCI_REGION_PREFETCH);
  71. sz -= pci_sz;
  72. bus_start += pci_sz;
  73. phys_start += pci_sz;
  74. }
  75. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  76. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  77. /* round up to the next largest power of two */
  78. if (gd->ram_size > pci_sz)
  79. sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  80. debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
  81. (u64)CONFIG_SYS_PCI_MEMORY_BUS,
  82. (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
  83. (u64)pci_sz);
  84. pci_set_region(r++,
  85. CONFIG_SYS_PCI_MEMORY_BUS,
  86. CONFIG_SYS_PCI_MEMORY_PHYS,
  87. pci_sz,
  88. PCI_REGION_MEM | PCI_REGION_MEMORY | \
  89. PCI_REGION_PREFETCH);
  90. #else
  91. pci_sz = 1ull << __ilog2_u64(sz);
  92. if (sz) {
  93. debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
  94. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  95. pci_set_region(r++, bus_start, phys_start, pci_sz,
  96. PCI_REGION_MEM | PCI_REGION_MEMORY | \
  97. PCI_REGION_PREFETCH);
  98. sz -= pci_sz;
  99. bus_start += pci_sz;
  100. phys_start += pci_sz;
  101. }
  102. #endif
  103. if (sz && (((u64)gd->ram_size) < (1ull << 32)))
  104. printf("Was not able to map all of memory via "
  105. "inbound windows -- %lld remaining\n", sz);
  106. return r - rgn_base;
  107. }
  108. void fsl_pci_init(struct pci_controller *hose)
  109. {
  110. u16 temp16;
  111. u32 temp32;
  112. int busno = hose->first_busno;
  113. int enabled;
  114. u16 ltssm;
  115. u8 temp8;
  116. int r;
  117. int bridge;
  118. int inbound = 0;
  119. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
  120. pci_dev_t dev = PCI_BDF(busno,0,0);
  121. /* Initialize ATMU registers based on hose regions and flags */
  122. volatile pot_t *po = &pci->pot[1]; /* skip 0 */
  123. volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */
  124. #ifdef DEBUG
  125. int neg_link_w;
  126. #endif
  127. for (r=0; r<hose->region_count; r++) {
  128. u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
  129. if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
  130. u32 flag = PIWAR_EN | PIWAR_LOCAL | \
  131. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  132. pi->pitar = (hose->regions[r].phys_start >> 12);
  133. pi->piwbar = (hose->regions[r].bus_start >> 12);
  134. #ifdef CONFIG_SYS_PCI_64BIT
  135. pi->piwbear = (hose->regions[r].bus_start >> 44);
  136. #else
  137. pi->piwbear = 0;
  138. #endif
  139. if (hose->regions[r].flags & PCI_REGION_PREFETCH)
  140. flag |= PIWAR_PF;
  141. pi->piwar = flag | sz;
  142. pi++;
  143. inbound = hose->regions[r].size > 0;
  144. } else { /* Outbound */
  145. po->powbar = (hose->regions[r].phys_start >> 12);
  146. po->potar = (hose->regions[r].bus_start >> 12);
  147. #ifdef CONFIG_SYS_PCI_64BIT
  148. po->potear = (hose->regions[r].bus_start >> 44);
  149. #else
  150. po->potear = 0;
  151. #endif
  152. if (hose->regions[r].flags & PCI_REGION_IO)
  153. po->powar = POWAR_EN | sz | \
  154. POWAR_IO_READ | POWAR_IO_WRITE;
  155. else
  156. po->powar = POWAR_EN | sz | \
  157. POWAR_MEM_READ | POWAR_MEM_WRITE;
  158. po++;
  159. }
  160. }
  161. pci_register_hose(hose);
  162. pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
  163. hose->current_busno = hose->first_busno;
  164. pci->pedr = 0xffffffff; /* Clear any errors */
  165. pci->peer = ~0x20140; /* Enable All Error Interupts except
  166. * - Master abort (pci)
  167. * - Master PERR (pci)
  168. * - ICCA (PCIe)
  169. */
  170. pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
  171. temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
  172. pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
  173. pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
  174. bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
  175. if ( bridge ) {
  176. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  177. enabled = ltssm >= PCI_LTSSM_L0;
  178. #ifdef CONFIG_FSL_PCIE_RESET
  179. if (ltssm == 1) {
  180. int i;
  181. debug("....PCIe link error. "
  182. "LTSSM=0x%02x.", ltssm);
  183. pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
  184. temp32 = pci->pdb_stat;
  185. udelay(100);
  186. debug(" Asserting PCIe reset @%x = %x\n",
  187. &pci->pdb_stat, pci->pdb_stat);
  188. pci->pdb_stat &= ~0x08000000; /* clear reset */
  189. asm("sync;isync");
  190. for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
  191. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  192. &ltssm);
  193. udelay(1000);
  194. debug("....PCIe link error. "
  195. "LTSSM=0x%02x.\n", ltssm);
  196. }
  197. enabled = ltssm >= PCI_LTSSM_L0;
  198. }
  199. #endif
  200. if (!enabled) {
  201. debug("....PCIE link error. Skipping scan."
  202. "LTSSM=0x%02x\n", ltssm);
  203. hose->last_busno = hose->first_busno;
  204. return;
  205. }
  206. pci->pme_msg_det = 0xffffffff;
  207. pci->pme_msg_int_en = 0xffffffff;
  208. #ifdef DEBUG
  209. pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
  210. neg_link_w = (temp16 & 0x3f0 ) >> 4;
  211. printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
  212. ltssm, neg_link_w);
  213. #endif
  214. hose->current_busno++; /* Start scan with secondary */
  215. pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
  216. }
  217. /* Use generic setup_device to initialize standard pci regs,
  218. * but do not allocate any windows since any BAR found (such
  219. * as PCSRBAR) is not in this cpu's memory space.
  220. */
  221. pciauto_setup_device(hose, dev, 0, hose->pci_mem,
  222. hose->pci_prefetch, hose->pci_io);
  223. if (inbound) {
  224. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
  225. pci_hose_write_config_word(hose, dev, PCI_COMMAND,
  226. temp16 | PCI_COMMAND_MEMORY);
  227. }
  228. #ifndef CONFIG_PCI_NOSCAN
  229. pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
  230. /* Programming Interface (PCI_CLASS_PROG)
  231. * 0 == pci host or pcie root-complex,
  232. * 1 == pci agent or pcie end-point
  233. */
  234. if (!temp8) {
  235. printf(" Scanning PCI bus %02x\n",
  236. hose->current_busno);
  237. hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
  238. } else {
  239. debug(" Not scanning PCI bus %02x. PI=%x\n",
  240. hose->current_busno, temp8);
  241. hose->last_busno = hose->current_busno;
  242. }
  243. if ( bridge ) { /* update limit regs and subordinate busno */
  244. pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
  245. }
  246. #else
  247. hose->last_busno = hose->current_busno;
  248. #endif
  249. /* Clear all error indications */
  250. if (bridge)
  251. pci->pme_msg_det = 0xffffffff;
  252. pci->pedr = 0xffffffff;
  253. pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
  254. if (temp16) {
  255. pci_hose_write_config_word(hose, dev,
  256. PCI_DSR, 0xffff);
  257. }
  258. pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
  259. if (temp16) {
  260. pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
  261. }
  262. }
  263. #ifdef CONFIG_OF_BOARD_SETUP
  264. #include <libfdt.h>
  265. #include <fdt_support.h>
  266. void ft_fsl_pci_setup(void *blob, const char *pci_alias,
  267. struct pci_controller *hose)
  268. {
  269. int off = fdt_path_offset(blob, pci_alias);
  270. if (off >= 0) {
  271. u32 bus_range[2];
  272. bus_range[0] = 0;
  273. bus_range[1] = hose->last_busno - hose->first_busno;
  274. fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
  275. fdt_pci_dma_ranges(blob, off, hose);
  276. }
  277. }
  278. #endif