pcnet.c 13 KB

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  1. /*
  2. * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
  3. *
  4. * This driver for AMD PCnet network controllers is derived from the
  5. * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <malloc.h>
  27. #include <net.h>
  28. #include <netdev.h>
  29. #include <asm/io.h>
  30. #include <pci.h>
  31. #if 0
  32. #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
  33. #endif
  34. #if PCNET_DEBUG_LEVEL > 0
  35. #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args)
  36. #if PCNET_DEBUG_LEVEL > 1
  37. #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args)
  38. #else
  39. #define PCNET_DEBUG2(fmt,args...)
  40. #endif
  41. #else
  42. #define PCNET_DEBUG1(fmt,args...)
  43. #define PCNET_DEBUG2(fmt,args...)
  44. #endif
  45. #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
  46. #error "Macro for PCnet chip version is not defined!"
  47. #endif
  48. /*
  49. * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  50. * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  51. * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  52. */
  53. #define PCNET_LOG_TX_BUFFERS 0
  54. #define PCNET_LOG_RX_BUFFERS 2
  55. #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
  56. #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
  57. #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
  58. #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
  59. #define PKT_BUF_SZ 1544
  60. /* The PCNET Rx and Tx ring descriptors. */
  61. struct pcnet_rx_head {
  62. u32 base;
  63. s16 buf_length;
  64. s16 status;
  65. u32 msg_length;
  66. u32 reserved;
  67. };
  68. struct pcnet_tx_head {
  69. u32 base;
  70. s16 length;
  71. s16 status;
  72. u32 misc;
  73. u32 reserved;
  74. };
  75. /* The PCNET 32-Bit initialization block, described in databook. */
  76. struct pcnet_init_block {
  77. u16 mode;
  78. u16 tlen_rlen;
  79. u8 phys_addr[6];
  80. u16 reserved;
  81. u32 filter[2];
  82. /* Receive and transmit ring base, along with extra bits. */
  83. u32 rx_ring;
  84. u32 tx_ring;
  85. u32 reserved2;
  86. };
  87. typedef struct pcnet_priv {
  88. struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  89. struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  90. struct pcnet_init_block init_block;
  91. /* Receive Buffer space */
  92. unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
  93. int cur_rx;
  94. int cur_tx;
  95. } pcnet_priv_t;
  96. static pcnet_priv_t *lp;
  97. /* Offsets from base I/O address for WIO mode */
  98. #define PCNET_RDP 0x10
  99. #define PCNET_RAP 0x12
  100. #define PCNET_RESET 0x14
  101. #define PCNET_BDP 0x16
  102. static u16 pcnet_read_csr (struct eth_device *dev, int index)
  103. {
  104. outw (index, dev->iobase + PCNET_RAP);
  105. return inw (dev->iobase + PCNET_RDP);
  106. }
  107. static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
  108. {
  109. outw (index, dev->iobase + PCNET_RAP);
  110. outw (val, dev->iobase + PCNET_RDP);
  111. }
  112. static u16 pcnet_read_bcr (struct eth_device *dev, int index)
  113. {
  114. outw (index, dev->iobase + PCNET_RAP);
  115. return inw (dev->iobase + PCNET_BDP);
  116. }
  117. static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
  118. {
  119. outw (index, dev->iobase + PCNET_RAP);
  120. outw (val, dev->iobase + PCNET_BDP);
  121. }
  122. static void pcnet_reset (struct eth_device *dev)
  123. {
  124. inw (dev->iobase + PCNET_RESET);
  125. }
  126. static int pcnet_check (struct eth_device *dev)
  127. {
  128. outw (88, dev->iobase + PCNET_RAP);
  129. return (inw (dev->iobase + PCNET_RAP) == 88);
  130. }
  131. static int pcnet_init (struct eth_device *dev, bd_t * bis);
  132. static int pcnet_send (struct eth_device *dev, volatile void *packet,
  133. int length);
  134. static int pcnet_recv (struct eth_device *dev);
  135. static void pcnet_halt (struct eth_device *dev);
  136. static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
  137. #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
  138. #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
  139. static struct pci_device_id supported[] = {
  140. {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
  141. {}
  142. };
  143. int pcnet_initialize (bd_t * bis)
  144. {
  145. pci_dev_t devbusfn;
  146. struct eth_device *dev;
  147. u16 command, status;
  148. int dev_nr = 0;
  149. PCNET_DEBUG1 ("\npcnet_initialize...\n");
  150. for (dev_nr = 0;; dev_nr++) {
  151. /*
  152. * Find the PCnet PCI device(s).
  153. */
  154. if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
  155. break;
  156. }
  157. /*
  158. * Allocate and pre-fill the device structure.
  159. */
  160. dev = (struct eth_device *) malloc (sizeof *dev);
  161. if (!dev) {
  162. printf("pcnet: Can not allocate memory\n");
  163. break;
  164. }
  165. memset(dev, 0, sizeof(*dev));
  166. dev->priv = (void *) devbusfn;
  167. sprintf (dev->name, "pcnet#%d", dev_nr);
  168. /*
  169. * Setup the PCI device.
  170. */
  171. pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
  172. (unsigned int *) &dev->iobase);
  173. dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
  174. dev->iobase &= ~0xf;
  175. PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
  176. dev->name, devbusfn, dev->iobase);
  177. command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
  178. pci_write_config_word (devbusfn, PCI_COMMAND, command);
  179. pci_read_config_word (devbusfn, PCI_COMMAND, &status);
  180. if ((status & command) != command) {
  181. printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
  182. free (dev);
  183. continue;
  184. }
  185. pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
  186. /*
  187. * Probe the PCnet chip.
  188. */
  189. if (pcnet_probe (dev, bis, dev_nr) < 0) {
  190. free (dev);
  191. continue;
  192. }
  193. /*
  194. * Setup device structure and register the driver.
  195. */
  196. dev->init = pcnet_init;
  197. dev->halt = pcnet_halt;
  198. dev->send = pcnet_send;
  199. dev->recv = pcnet_recv;
  200. eth_register (dev);
  201. }
  202. udelay (10 * 1000);
  203. return dev_nr;
  204. }
  205. static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
  206. {
  207. int chip_version;
  208. char *chipname;
  209. #ifdef PCNET_HAS_PROM
  210. int i;
  211. #endif
  212. /* Reset the PCnet controller */
  213. pcnet_reset (dev);
  214. /* Check if register access is working */
  215. if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
  216. printf ("%s: CSR register access check failed\n", dev->name);
  217. return -1;
  218. }
  219. /* Identify the chip */
  220. chip_version =
  221. pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
  222. if ((chip_version & 0xfff) != 0x003)
  223. return -1;
  224. chip_version = (chip_version >> 12) & 0xffff;
  225. switch (chip_version) {
  226. case 0x2621:
  227. chipname = "PCnet/PCI II 79C970A"; /* PCI */
  228. break;
  229. #ifdef CONFIG_PCNET_79C973
  230. case 0x2625:
  231. chipname = "PCnet/FAST III 79C973"; /* PCI */
  232. break;
  233. #endif
  234. #ifdef CONFIG_PCNET_79C975
  235. case 0x2627:
  236. chipname = "PCnet/FAST III 79C975"; /* PCI */
  237. break;
  238. #endif
  239. default:
  240. printf ("%s: PCnet version %#x not supported\n",
  241. dev->name, chip_version);
  242. return -1;
  243. }
  244. PCNET_DEBUG1 ("AMD %s\n", chipname);
  245. #ifdef PCNET_HAS_PROM
  246. /*
  247. * In most chips, after a chip reset, the ethernet address is read from
  248. * the station address PROM at the base address and programmed into the
  249. * "Physical Address Registers" CSR12-14.
  250. */
  251. for (i = 0; i < 3; i++) {
  252. unsigned int val;
  253. val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
  254. /* There may be endianness issues here. */
  255. dev->enetaddr[2 * i] = val & 0x0ff;
  256. dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
  257. }
  258. #endif /* PCNET_HAS_PROM */
  259. return 0;
  260. }
  261. static int pcnet_init (struct eth_device *dev, bd_t * bis)
  262. {
  263. int i, val;
  264. u32 addr;
  265. PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
  266. /* Switch pcnet to 32bit mode */
  267. pcnet_write_bcr (dev, 20, 2);
  268. #ifdef CONFIG_PN62
  269. /* Setup LED registers */
  270. val = pcnet_read_bcr (dev, 2) | 0x1000;
  271. pcnet_write_bcr (dev, 2, val); /* enable LEDPE */
  272. pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
  273. pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
  274. pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
  275. pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
  276. #endif
  277. /* Set/reset autoselect bit */
  278. val = pcnet_read_bcr (dev, 2) & ~2;
  279. val |= 2;
  280. pcnet_write_bcr (dev, 2, val);
  281. /* Enable auto negotiate, setup, disable fd */
  282. val = pcnet_read_bcr (dev, 32) & ~0x98;
  283. val |= 0x20;
  284. pcnet_write_bcr (dev, 32, val);
  285. /*
  286. * We only maintain one structure because the drivers will never
  287. * be used concurrently. In 32bit mode the RX and TX ring entries
  288. * must be aligned on 16-byte boundaries.
  289. */
  290. if (lp == NULL) {
  291. addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
  292. addr = (addr + 0xf) & ~0xf;
  293. lp = (pcnet_priv_t *) addr;
  294. }
  295. lp->init_block.mode = cpu_to_le16 (0x0000);
  296. lp->init_block.filter[0] = 0x00000000;
  297. lp->init_block.filter[1] = 0x00000000;
  298. /*
  299. * Initialize the Rx ring.
  300. */
  301. lp->cur_rx = 0;
  302. for (i = 0; i < RX_RING_SIZE; i++) {
  303. lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
  304. lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
  305. lp->rx_ring[i].status = cpu_to_le16 (0x8000);
  306. PCNET_DEBUG1
  307. ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
  308. lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
  309. lp->rx_ring[i].status);
  310. }
  311. /*
  312. * Initialize the Tx ring. The Tx buffer address is filled in as
  313. * needed, but we do need to clear the upper ownership bit.
  314. */
  315. lp->cur_tx = 0;
  316. for (i = 0; i < TX_RING_SIZE; i++) {
  317. lp->tx_ring[i].base = 0;
  318. lp->tx_ring[i].status = 0;
  319. }
  320. /*
  321. * Setup Init Block.
  322. */
  323. PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
  324. for (i = 0; i < 6; i++) {
  325. lp->init_block.phys_addr[i] = dev->enetaddr[i];
  326. PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
  327. }
  328. lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
  329. RX_RING_LEN_BITS);
  330. lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
  331. lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
  332. PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
  333. lp->init_block.tlen_rlen,
  334. lp->init_block.rx_ring, lp->init_block.tx_ring);
  335. /*
  336. * Tell the controller where the Init Block is located.
  337. */
  338. addr = PCI_TO_MEM (dev, &lp->init_block);
  339. pcnet_write_csr (dev, 1, addr & 0xffff);
  340. pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
  341. pcnet_write_csr (dev, 4, 0x0915);
  342. pcnet_write_csr (dev, 0, 0x0001); /* start */
  343. /* Wait for Init Done bit */
  344. for (i = 10000; i > 0; i--) {
  345. if (pcnet_read_csr (dev, 0) & 0x0100)
  346. break;
  347. udelay (10);
  348. }
  349. if (i <= 0) {
  350. printf ("%s: TIMEOUT: controller init failed\n", dev->name);
  351. pcnet_reset (dev);
  352. return -1;
  353. }
  354. /*
  355. * Finally start network controller operation.
  356. */
  357. pcnet_write_csr (dev, 0, 0x0002);
  358. return 0;
  359. }
  360. static int pcnet_send (struct eth_device *dev, volatile void *packet,
  361. int pkt_len)
  362. {
  363. int i, status;
  364. struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
  365. PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
  366. packet);
  367. /* Wait for completion by testing the OWN bit */
  368. for (i = 1000; i > 0; i--) {
  369. status = le16_to_cpu (entry->status);
  370. if ((status & 0x8000) == 0)
  371. break;
  372. udelay (100);
  373. PCNET_DEBUG2 (".");
  374. }
  375. if (i <= 0) {
  376. printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
  377. dev->name, lp->cur_tx, status);
  378. pkt_len = 0;
  379. goto failure;
  380. }
  381. /*
  382. * Setup Tx ring. Caution: the write order is important here,
  383. * set the status with the "ownership" bits last.
  384. */
  385. status = 0x8300;
  386. entry->length = le16_to_cpu (-pkt_len);
  387. entry->misc = 0x00000000;
  388. entry->base = PCI_TO_MEM_LE (dev, packet);
  389. entry->status = le16_to_cpu (status);
  390. /* Trigger an immediate send poll. */
  391. pcnet_write_csr (dev, 0, 0x0008);
  392. failure:
  393. if (++lp->cur_tx >= TX_RING_SIZE)
  394. lp->cur_tx = 0;
  395. PCNET_DEBUG2 ("done\n");
  396. return pkt_len;
  397. }
  398. static int pcnet_recv (struct eth_device *dev)
  399. {
  400. struct pcnet_rx_head *entry;
  401. int pkt_len = 0;
  402. u16 status;
  403. while (1) {
  404. entry = &lp->rx_ring[lp->cur_rx];
  405. /*
  406. * If we own the next entry, it's a new packet. Send it up.
  407. */
  408. if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
  409. break;
  410. }
  411. status >>= 8;
  412. if (status != 0x03) { /* There was an error. */
  413. printf ("%s: Rx%d", dev->name, lp->cur_rx);
  414. PCNET_DEBUG1 (" (status=0x%x)", status);
  415. if (status & 0x20)
  416. printf (" Frame");
  417. if (status & 0x10)
  418. printf (" Overflow");
  419. if (status & 0x08)
  420. printf (" CRC");
  421. if (status & 0x04)
  422. printf (" Fifo");
  423. printf (" Error\n");
  424. entry->status &= le16_to_cpu (0x03ff);
  425. } else {
  426. pkt_len =
  427. (le32_to_cpu (entry->msg_length) & 0xfff) - 4;
  428. if (pkt_len < 60) {
  429. printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
  430. } else {
  431. NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
  432. PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
  433. lp->cur_rx, pkt_len,
  434. lp->rx_buf[lp->cur_rx]);
  435. }
  436. }
  437. entry->status |= cpu_to_le16 (0x8000);
  438. if (++lp->cur_rx >= RX_RING_SIZE)
  439. lp->cur_rx = 0;
  440. }
  441. return pkt_len;
  442. }
  443. static void pcnet_halt (struct eth_device *dev)
  444. {
  445. int i;
  446. PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
  447. /* Reset the PCnet controller */
  448. pcnet_reset (dev);
  449. /* Wait for Stop bit */
  450. for (i = 1000; i > 0; i--) {
  451. if (pcnet_read_csr (dev, 0) & 0x4)
  452. break;
  453. udelay (10);
  454. }
  455. if (i <= 0) {
  456. printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
  457. }
  458. }