cpu.c 3.3 KB

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  1. /*
  2. *
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <watchdog.h>
  29. #include <command.h>
  30. #include <netdev.h>
  31. #include <asm/immap.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
  34. {
  35. volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  36. gptmr->pre = 10;
  37. gptmr->cnt = 1;
  38. /* enable watchdog, set timeout to 0 and wait */
  39. gptmr->mode = GPT_TMS_SGPIO;
  40. gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
  41. /* we don't return! */
  42. return 1;
  43. };
  44. int checkcpu(void)
  45. {
  46. volatile siu_t *siu = (siu_t *) MMAP_SIU;
  47. u16 id = 0;
  48. puts("CPU: ");
  49. switch ((siu->jtagid & 0x000FF000) >> 12) {
  50. case 0x0C:
  51. id = 5485;
  52. break;
  53. case 0x0D:
  54. id = 5484;
  55. break;
  56. case 0x0E:
  57. id = 5483;
  58. break;
  59. case 0x0F:
  60. id = 5482;
  61. break;
  62. case 0x10:
  63. id = 5481;
  64. break;
  65. case 0x11:
  66. id = 5480;
  67. break;
  68. case 0x12:
  69. id = 5475;
  70. break;
  71. case 0x13:
  72. id = 5474;
  73. break;
  74. case 0x14:
  75. id = 5473;
  76. break;
  77. case 0x15:
  78. id = 5472;
  79. break;
  80. case 0x16:
  81. id = 5471;
  82. break;
  83. case 0x17:
  84. id = 5470;
  85. break;
  86. }
  87. if (id) {
  88. char buf1[32], buf2[32];
  89. printf("Freescale MCF%d\n", id);
  90. printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
  91. strmhz(buf1, gd->cpu_clk),
  92. strmhz(buf2, gd->bus_clk));
  93. }
  94. return 0;
  95. };
  96. #if defined(CONFIG_HW_WATCHDOG)
  97. /* Called by macro WATCHDOG_RESET */
  98. void hw_watchdog_reset(void)
  99. {
  100. volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  101. gptmr->ocpw = 0xa5;
  102. }
  103. int watchdog_disable(void)
  104. {
  105. volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  106. /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
  107. gptmr->mode = 0;
  108. gptmr->ctrl = 0;
  109. puts("WATCHDOG:disabled\n");
  110. return (0);
  111. }
  112. int watchdog_init(void)
  113. {
  114. volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  115. gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
  116. gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
  117. gptmr->mode = GPT_TMS_SGPIO;
  118. gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
  119. puts("WATCHDOG:enabled\n");
  120. return (0);
  121. }
  122. #endif /* CONFIG_HW_WATCHDOG */
  123. #if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
  124. /* Default initializations for MCFFEC controllers. To override,
  125. * create a board-specific function called:
  126. * int board_eth_init(bd_t *bis)
  127. */
  128. int cpu_eth_init(bd_t *bis)
  129. {
  130. #if defined(CONFIG_FSLDMAFEC)
  131. mcdmafec_initialize(bis);
  132. #endif
  133. #if defined(CONFIG_MCFFEC)
  134. mcffec_initialize(bis);
  135. #endif
  136. return 0;
  137. }
  138. #endif