oftree.dts 4.7 KB

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  1. /*
  2. * MPC8641 HPCN Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8641HPCN";
  13. compatible = "mpc86xx";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. linux,phandle = <100>;
  17. cpus {
  18. #cpus = <2>;
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. linux,phandle = <200>;
  22. PowerPC,8641@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <8000>; // L1, 32K
  28. i-cache-size = <8000>; // L1, 32K
  29. timebase-frequency = <0>; // 33 MHz, from uboot
  30. bus-frequency = <0>; // From uboot
  31. clock-frequency = <0>; // From uboot
  32. 32-bit;
  33. linux,phandle = <201>;
  34. linux,boot-cpu;
  35. };
  36. PowerPC,8641@1 {
  37. device_type = "cpu";
  38. reg = <1>;
  39. d-cache-line-size = <20>; // 32 bytes
  40. i-cache-line-size = <20>; // 32 bytes
  41. d-cache-size = <8000>; // L1, 32K
  42. i-cache-size = <8000>; // L1, 32K
  43. timebase-frequency = <0>; // 33 MHz, from uboot
  44. bus-frequency = <0>; // From uboot
  45. clock-frequency = <0>; // From uboot
  46. 32-bit;
  47. linux,phandle = <202>;
  48. };
  49. };
  50. memory {
  51. device_type = "memory";
  52. linux,phandle = <300>;
  53. reg = <00000000 40000000>; // 1G at 0x0, replaced by uboot
  54. };
  55. soc8641@f8000000 {
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. #interrupt-cells = <2>;
  59. device_type = "soc";
  60. ranges = <0 f8000000 00100000>;
  61. reg = <f8000000 00100000>; // CCSRBAR 1M
  62. bus-frequency = <0>;
  63. i2c@3000 {
  64. device_type = "i2c";
  65. compatible = "fsl-i2c";
  66. reg = <3000 100>;
  67. interrupts = <2b 0>;
  68. interrupt-parent = <40000>;
  69. dfsrr;
  70. };
  71. i2c@3100 {
  72. device_type = "i2c";
  73. compatible = "fsl-i2c";
  74. reg = <3100 100>;
  75. interrupts = <2b 0>;
  76. interrupt-parent = <40000>;
  77. dfsrr;
  78. };
  79. mdio@24520 {
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. device_type = "mdio";
  83. compatible = "gianfar";
  84. reg = <24520 20>;
  85. linux,phandle = <24520>;
  86. ethernet-phy@0 {
  87. linux,phandle = <2452000>;
  88. interrupt-parent = <40000>;
  89. interrupts = <a 0>;
  90. reg = <0>;
  91. device_type = "ethernet-phy";
  92. };
  93. ethernet-phy@1 {
  94. linux,phandle = <2452001>;
  95. interrupt-parent = <40000>;
  96. interrupts = <a 0>;
  97. reg = <1>;
  98. device_type = "ethernet-phy";
  99. };
  100. ethernet-phy@2 {
  101. linux,phandle = <2452002>;
  102. interrupt-parent = <40000>;
  103. interrupts = <a 0>;
  104. reg = <2>;
  105. device_type = "ethernet-phy";
  106. };
  107. ethernet-phy@3 {
  108. linux,phandle = <2452003>;
  109. interrupt-parent = <40000>;
  110. interrupts = <a 0>;
  111. reg = <3>;
  112. device_type = "ethernet-phy";
  113. };
  114. };
  115. ethernet@24000 {
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. device_type = "network";
  119. model = "TSEC";
  120. compatible = "gianfar";
  121. reg = <24000 1000>;
  122. address = [ 00 E0 0C 00 73 00 ];
  123. interrupts = <1d 3 1e 3 22 3>;
  124. interrupt-parent = <40000>;
  125. phy-handle = <2452000>;
  126. };
  127. ethernet@25000 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. device_type = "network";
  131. model = "TSEC";
  132. compatible = "gianfar";
  133. reg = <25000 1000>;
  134. address = [ 00 E0 0C 00 73 01 ];
  135. interrupts = <23 3 24 3 28 3>;
  136. interrupt-parent = <40000>;
  137. phy-handle = <2452001>;
  138. };
  139. ethernet@26000 {
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. device_type = "network";
  143. model = "TSEC";
  144. compatible = "gianfar";
  145. reg = <26000 1000>;
  146. address = [ 00 E0 0C 00 02 FD ];
  147. interrupts = <1F 3 20 3 21 3>;
  148. interrupt-parent = <40000>;
  149. phy-handle = <2452002>;
  150. };
  151. ethernet@27000 {
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. device_type = "network";
  155. model = "TSEC";
  156. compatible = "gianfar";
  157. reg = <27000 1000>;
  158. address = [ 00 E0 0C 00 03 FD ];
  159. interrupts = <25 3 26 3 27 3>;
  160. interrupt-parent = <40000>;
  161. phy-handle = <2452003>;
  162. };
  163. serial@4500 {
  164. device_type = "serial";
  165. compatible = "ns16550";
  166. reg = <4500 100>; // reg base, size
  167. clock-frequency = <0>; // should we fill in in uboot?
  168. interrupts = <2a 3>;
  169. interrupt-parent = <40000>;
  170. };
  171. serial@4600 {
  172. device_type = "serial";
  173. compatible = "ns16550";
  174. reg = <4600 100>; // reg base, size
  175. clock-frequency = <0>; // should we fill in in uboot?
  176. interrupts = <2a 3>;
  177. interrupt-parent = <40000>;
  178. };
  179. pic@40000 {
  180. linux,phandle = <40000>;
  181. clock-frequency = <0>;
  182. interrupt-controller;
  183. #address-cells = <0>;
  184. #interrupt-cells = <2>;
  185. reg = <40000 40000>;
  186. built-in;
  187. compatible = "chrp,open-pic";
  188. device_type = "open-pic";
  189. big-endian;
  190. };
  191. };
  192. };