ddr1_2_dimm_params.h 2.4 KB

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  1. /*
  2. * Copyright 2008 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #ifndef DDR2_DIMM_PARAMS_H
  9. #define DDR2_DIMM_PARAMS_H
  10. /* Parameters for a DDR2 dimm computed from the SPD */
  11. typedef struct dimm_params_s {
  12. /* DIMM organization parameters */
  13. char mpart[19]; /* guaranteed null terminated */
  14. unsigned int n_ranks;
  15. unsigned long long rank_density;
  16. unsigned long long capacity;
  17. unsigned int data_width;
  18. unsigned int primary_sdram_width;
  19. unsigned int ec_sdram_width;
  20. unsigned int registered_dimm;
  21. /* SDRAM device parameters */
  22. unsigned int n_row_addr;
  23. unsigned int n_col_addr;
  24. unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
  25. unsigned int n_banks_per_sdram_device;
  26. unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
  27. unsigned int row_density;
  28. /* used in computing base address of DIMMs */
  29. unsigned long long base_address;
  30. /* DIMM timing parameters */
  31. /*
  32. * SDRAM clock periods
  33. * The range for these are 1000-10000 so a short should be sufficient
  34. */
  35. unsigned int tCKmin_X_ps;
  36. unsigned int tCKmin_X_minus_1_ps;
  37. unsigned int tCKmin_X_minus_2_ps;
  38. unsigned int tCKmax_ps;
  39. /* SPD-defined CAS latencies */
  40. unsigned int caslat_X;
  41. unsigned int caslat_X_minus_1;
  42. unsigned int caslat_X_minus_2;
  43. unsigned int caslat_lowest_derated; /* Derated CAS latency */
  44. /* basic timing parameters */
  45. unsigned int tRCD_ps;
  46. unsigned int tRP_ps;
  47. unsigned int tRAS_ps;
  48. unsigned int tWR_ps; /* maximum = 63750 ps */
  49. unsigned int tWTR_ps; /* maximum = 63750 ps */
  50. unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
  51. = 511750 ps */
  52. unsigned int tRRD_ps; /* maximum = 63750 ps */
  53. unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
  54. unsigned int refresh_rate_ps;
  55. unsigned int tIS_ps; /* byte 32, spd->ca_setup */
  56. unsigned int tIH_ps; /* byte 33, spd->ca_hold */
  57. unsigned int tDS_ps; /* byte 34, spd->data_setup */
  58. unsigned int tDH_ps; /* byte 35, spd->data_hold */
  59. unsigned int tRTP_ps; /* byte 38, spd->trtp */
  60. unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
  61. unsigned int tQHS_ps; /* byte 45, spd->tqhs */
  62. } dimm_params_t;
  63. extern unsigned int ddr_compute_dimm_parameters(
  64. const generic_spd_eeprom_t *spd,
  65. dimm_params_t *pdimm,
  66. unsigned int dimm_number);
  67. #endif