flash.c 12 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  28. /*
  29. * CPU to flash interface is 32-bit, so make declaration accordingly
  30. */
  31. typedef unsigned long FLASH_PORT_WIDTH;
  32. typedef volatile unsigned long FLASH_PORT_WIDTHV;
  33. #define FPW FLASH_PORT_WIDTH
  34. #define FPWV FLASH_PORT_WIDTHV
  35. #define FLASH_CYCLE1 0x0555
  36. #define FLASH_CYCLE2 0x02aa
  37. /*-----------------------------------------------------------------------
  38. * Functions
  39. */
  40. static ulong flash_get_size(FPWV *addr, flash_info_t *info);
  41. static void flash_reset(flash_info_t *info);
  42. static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
  43. static flash_info_t *flash_get_info(ulong base);
  44. /*-----------------------------------------------------------------------
  45. * flash_init()
  46. *
  47. * sets up flash_info and returns size of FLASH (bytes)
  48. */
  49. unsigned long flash_init (void)
  50. {
  51. unsigned long size = 0;
  52. extern void flash_preinit(void);
  53. ulong flashbase = CFG_FLASH_BASE;
  54. flash_preinit();
  55. /* Init: no FLASHes known */
  56. memset(&flash_info[0], 0, sizeof(flash_info_t));
  57. flash_info[0].size =
  58. flash_get_size((FPW *)flashbase, &flash_info[0]);
  59. size = flash_info[0].size;
  60. #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  61. /* monitor protection ON by default */
  62. flash_protect(FLAG_PROTECT_SET,
  63. CFG_MONITOR_BASE,
  64. CFG_MONITOR_BASE+monitor_flash_len-1,
  65. flash_get_info(CFG_MONITOR_BASE));
  66. #endif
  67. #ifdef CFG_ENV_IS_IN_FLASH
  68. /* ENV protection ON by default */
  69. flash_protect(FLAG_PROTECT_SET,
  70. CFG_ENV_ADDR,
  71. CFG_ENV_ADDR+CFG_ENV_SIZE-1,
  72. flash_get_info(CFG_ENV_ADDR));
  73. #endif
  74. return size ? size : 1;
  75. }
  76. /*-----------------------------------------------------------------------
  77. */
  78. static void flash_reset(flash_info_t *info)
  79. {
  80. FPWV *base = (FPWV *)(info->start[0]);
  81. /* Put FLASH back in read mode */
  82. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
  83. *base = (FPW)0x00FF00FF; /* Intel Read Mode */
  84. else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
  85. *base = (FPW)0x00F000F0; /* AMD Read Mode */
  86. }
  87. /*-----------------------------------------------------------------------
  88. */
  89. static flash_info_t *flash_get_info(ulong base)
  90. {
  91. int i;
  92. flash_info_t * info;
  93. for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
  94. info = & flash_info[i];
  95. if (info->size && info->start[0] <= base &&
  96. base <= info->start[0] + info->size - 1)
  97. break;
  98. }
  99. return i == CFG_MAX_FLASH_BANKS ? 0 : info;
  100. }
  101. /*-----------------------------------------------------------------------
  102. */
  103. void flash_print_info (flash_info_t *info)
  104. {
  105. int i;
  106. if (info->flash_id == FLASH_UNKNOWN) {
  107. printf ("missing or unknown FLASH type\n");
  108. return;
  109. }
  110. switch (info->flash_id & FLASH_VENDMASK) {
  111. case FLASH_MAN_AMD: printf ("AMD "); break;
  112. case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
  113. case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
  114. case FLASH_MAN_SST: printf ("SST "); break;
  115. case FLASH_MAN_STM: printf ("STM "); break;
  116. case FLASH_MAN_INTEL: printf ("INTEL "); break;
  117. default: printf ("Unknown Vendor "); break;
  118. }
  119. switch (info->flash_id & FLASH_TYPEMASK) {
  120. case FLASH_AMLV128U:
  121. printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
  122. break;
  123. case FLASH_AM160B:
  124. printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
  125. break;
  126. default:
  127. printf ("Unknown Chip Type\n");
  128. break;
  129. }
  130. printf (" Size: %ld MB in %d Sectors\n",
  131. info->size >> 20,
  132. info->sector_count);
  133. printf (" Sector Start Addresses:");
  134. for (i=0; i<info->sector_count; ++i) {
  135. if ((i % 5) == 0) {
  136. printf ("\n ");
  137. }
  138. printf (" %08lX%s",
  139. info->start[i],
  140. info->protect[i] ? " (RO)" : " ");
  141. }
  142. printf ("\n");
  143. return;
  144. }
  145. /*-----------------------------------------------------------------------
  146. */
  147. /*
  148. * The following code cannot be run from FLASH!
  149. */
  150. ulong flash_get_size (FPWV *addr, flash_info_t *info)
  151. {
  152. int i;
  153. ulong base = (ulong)addr;
  154. /* Write auto select command: read Manufacturer ID */
  155. /* Write auto select command sequence and test FLASH answer */
  156. addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
  157. addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
  158. addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
  159. /* The manufacturer codes are only 1 byte, so just use 1 byte.
  160. * This works for any bus width and any FLASH device width.
  161. */
  162. udelay(100);
  163. switch (addr[0] & 0xff) {
  164. case (uchar)AMD_MANUFACT:
  165. debug ("Manufacturer: AMD (Spansion)\n");
  166. info->flash_id = FLASH_MAN_AMD;
  167. break;
  168. case (uchar)INTEL_MANUFACT:
  169. debug ("Manufacturer: Intel (not supported yet)\n");
  170. info->flash_id = FLASH_MAN_INTEL;
  171. break;
  172. default:
  173. info->flash_id = FLASH_UNKNOWN;
  174. info->sector_count = 0;
  175. info->size = 0;
  176. break;
  177. }
  178. /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
  179. if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
  180. case (FPW)AMD_ID_LV160B:
  181. debug ("Chip: AM29LV160MB\n");
  182. info->flash_id += FLASH_AM160B;
  183. info->sector_count = 35;
  184. info->size = 0x00400000;
  185. /*
  186. * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
  187. * the other ones are 64 kB
  188. */
  189. info->start[0] = base + 0x00000000;
  190. info->start[1] = base + 0x00008000;
  191. info->start[2] = base + 0x0000C000;
  192. info->start[3] = base + 0x00010000;
  193. for( i = 4; i < info->sector_count; i++ )
  194. info->start[i] =
  195. base + (i * 2 * (64 << 10)) - 0x00060000;
  196. break; /* => 4 MB */
  197. case AMD_ID_MIRROR:
  198. debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
  199. addr[14], addr[15]);
  200. switch(addr[14]) {
  201. case AMD_ID_LV128U_2:
  202. if (addr[15] != AMD_ID_LV128U_3) {
  203. debug ("Chip: AM29LVxxxM -> unknown\n");
  204. info->flash_id = FLASH_UNKNOWN;
  205. info->sector_count = 0;
  206. info->size = 0;
  207. } else {
  208. debug ("Chip: AM29LV128M\n");
  209. info->flash_id += FLASH_AMLV128U;
  210. info->sector_count = 256;
  211. info->size = 0x02000000;
  212. for (i = 0; i < info->sector_count; i++) {
  213. info->start[i] = base;
  214. base += 0x20000;
  215. }
  216. }
  217. break; /* => 32 MB */
  218. default:
  219. debug ("Chip: *** unknown ***\n");
  220. info->flash_id = FLASH_UNKNOWN;
  221. info->sector_count = 0;
  222. info->size = 0;
  223. break;
  224. }
  225. break;
  226. default:
  227. info->flash_id = FLASH_UNKNOWN;
  228. info->sector_count = 0;
  229. info->size = 0;
  230. }
  231. /* Put FLASH back in read mode */
  232. flash_reset(info);
  233. return (info->size);
  234. }
  235. /*-----------------------------------------------------------------------
  236. */
  237. int flash_erase (flash_info_t *info, int s_first, int s_last)
  238. {
  239. vu_long *addr = (vu_long*)(info->start[0]);
  240. int flag, prot, sect, l_sect;
  241. ulong start, now, last;
  242. debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
  243. if ((s_first < 0) || (s_first > s_last)) {
  244. if (info->flash_id == FLASH_UNKNOWN) {
  245. printf ("- missing\n");
  246. } else {
  247. printf ("- no sectors to erase\n");
  248. }
  249. return 1;
  250. }
  251. if ((info->flash_id == FLASH_UNKNOWN) ||
  252. (info->flash_id > FLASH_AMD_COMP)) {
  253. printf ("Can't erase unknown flash type %08lx - aborted\n",
  254. info->flash_id);
  255. return 1;
  256. }
  257. prot = 0;
  258. for (sect=s_first; sect<=s_last; ++sect) {
  259. if (info->protect[sect]) {
  260. prot++;
  261. }
  262. }
  263. if (prot) {
  264. printf ("- Warning: %d protected sectors will not be erased!\n",
  265. prot);
  266. } else {
  267. printf ("\n");
  268. }
  269. l_sect = -1;
  270. /* Disable interrupts which might cause a timeout here */
  271. flag = disable_interrupts();
  272. addr[0x0555] = 0x00AA00AA;
  273. addr[0x02AA] = 0x00550055;
  274. addr[0x0555] = 0x00800080;
  275. addr[0x0555] = 0x00AA00AA;
  276. addr[0x02AA] = 0x00550055;
  277. /* Start erase on unprotected sectors */
  278. for (sect = s_first; sect<=s_last; sect++) {
  279. if (info->protect[sect] == 0) { /* not protected */
  280. addr = (vu_long*)(info->start[sect]);
  281. addr[0] = 0x00300030;
  282. l_sect = sect;
  283. }
  284. }
  285. /* re-enable interrupts if necessary */
  286. if (flag)
  287. enable_interrupts();
  288. /* wait at least 80us - let's wait 1 ms */
  289. udelay (1000);
  290. /*
  291. * We wait for the last triggered sector
  292. */
  293. if (l_sect < 0)
  294. goto DONE;
  295. start = get_timer (0);
  296. last = start;
  297. addr = (vu_long*)(info->start[l_sect]);
  298. while ((addr[0] & 0x00800080) != 0x00800080) {
  299. if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
  300. printf ("Timeout\n");
  301. return 1;
  302. }
  303. /* show that we're waiting */
  304. if ((now - last) > 1000) { /* every second */
  305. putc ('.');
  306. last = now;
  307. }
  308. }
  309. DONE:
  310. /* reset to read mode */
  311. addr = (volatile unsigned long *)info->start[0];
  312. addr[0] = 0x00F000F0; /* reset bank */
  313. printf (" done\n");
  314. return 0;
  315. }
  316. /*-----------------------------------------------------------------------
  317. * Copy memory to flash, returns:
  318. * 0 - OK
  319. * 1 - write timeout
  320. * 2 - Flash not erased
  321. */
  322. int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  323. {
  324. ulong cp, wp, data;
  325. int i, l, rc;
  326. /*
  327. * Get lower word aligned address. Assumes 32 bit flash bus width.
  328. */
  329. wp = (addr & ~3);
  330. /*
  331. * handle unaligned start bytes
  332. */
  333. if ((l = addr - wp) != 0) {
  334. data = 0;
  335. for (i=0, cp=wp; i<l; ++i, ++cp) {
  336. data = (data << 8) | (*(uchar *)cp);
  337. }
  338. for (; i<4 && cnt>0; ++i) {
  339. data = (data << 8) | *src++;
  340. --cnt;
  341. ++cp;
  342. }
  343. for (; cnt==0 && i<4; ++i, ++cp) {
  344. data = (data << 8) | (*(uchar *)cp);
  345. }
  346. if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
  347. return (rc);
  348. }
  349. wp += 4;
  350. }
  351. /*
  352. * handle word aligned part
  353. */
  354. while (cnt >= 4) {
  355. data = 0;
  356. for (i=0; i<4; ++i) {
  357. data = (data << 8) | *src++;
  358. }
  359. if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
  360. return (rc);
  361. }
  362. wp += 4;
  363. cnt -= 4;
  364. }
  365. if (cnt == 0) {
  366. return (0);
  367. }
  368. /*
  369. * handle unaligned tail bytes
  370. */
  371. data = 0;
  372. for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
  373. data = (data << 8) | *src++;
  374. --cnt;
  375. }
  376. for (; i<4; ++i, ++cp) {
  377. data = (data << 8) | (*(uchar *)cp);
  378. }
  379. return (write_word_amd(info, (FPW *)wp, data));
  380. }
  381. /*-----------------------------------------------------------------------
  382. * Write a word to Flash for AMD FLASH
  383. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  384. * (not an individual chip) is.
  385. *
  386. * returns:
  387. * 0 - OK
  388. * 1 - write timeout
  389. * 2 - Flash not erased
  390. */
  391. static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
  392. {
  393. ulong start;
  394. int flag;
  395. FPWV *base; /* first address in flash bank */
  396. /* Check if Flash is (sufficiently) erased */
  397. if ((*dest & data) != data) {
  398. return (2);
  399. }
  400. base = (FPWV *)(info->start[0]);
  401. /* Disable interrupts which might cause a timeout here */
  402. flag = disable_interrupts();
  403. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  404. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  405. base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
  406. *dest = data; /* start programming the data */
  407. /* re-enable interrupts if necessary */
  408. if (flag)
  409. enable_interrupts();
  410. start = get_timer (0);
  411. /* data polling for D7 */
  412. while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
  413. if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  414. *dest = (FPW)0x00F000F0; /* reset bank */
  415. return (1);
  416. }
  417. }
  418. return (0);
  419. }