pci_cfg.c 4.5 KB

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  1. /*
  2. * Copyright 2009 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/fsl_law.h>
  24. #include <pci.h>
  25. struct pci_info {
  26. u16 cfg;
  27. };
  28. /* The cfg field is a bit mask in which each bit represents the value of
  29. * cfg_IO_ports[] signal and the bit is set if the interface would be
  30. * enabled based on the value of cfg_IO_ports[] signal
  31. *
  32. * On MPC86xx/PQ3 based systems:
  33. * we extract cfg_IO_ports from GUTS register PORDEVSR
  34. *
  35. * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
  36. * without PCIe)
  37. */
  38. #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
  39. static struct pci_info pci_config_info[] =
  40. {
  41. [LAW_TRGT_IF_PCI] = {
  42. .cfg = 0,
  43. },
  44. };
  45. #elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
  46. static struct pci_info pci_config_info[] =
  47. {
  48. [LAW_TRGT_IF_PCI] = {
  49. .cfg = 0,
  50. },
  51. };
  52. #elif defined(CONFIG_MPC8536)
  53. static struct pci_info pci_config_info[] =
  54. {
  55. [LAW_TRGT_IF_PCI] = {
  56. .cfg = 0,
  57. },
  58. [LAW_TRGT_IF_PCIE_1] = {
  59. .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
  60. },
  61. [LAW_TRGT_IF_PCIE_2] = {
  62. .cfg = (1 << 5) | (1 << 7),
  63. },
  64. [LAW_TRGT_IF_PCIE_3] = {
  65. .cfg = (1 << 7),
  66. },
  67. };
  68. #elif defined(CONFIG_MPC8544)
  69. static struct pci_info pci_config_info[] =
  70. {
  71. [LAW_TRGT_IF_PCI] = {
  72. .cfg = 0,
  73. },
  74. [LAW_TRGT_IF_PCIE_1] = {
  75. .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
  76. (1 << 6) | (1 << 7),
  77. },
  78. [LAW_TRGT_IF_PCIE_2] = {
  79. .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
  80. },
  81. [LAW_TRGT_IF_PCIE_3] = {
  82. .cfg = (1 << 6) | (1 << 7),
  83. },
  84. };
  85. #elif defined(CONFIG_MPC8548)
  86. static struct pci_info pci_config_info[] =
  87. {
  88. [LAW_TRGT_IF_PCI_1] = {
  89. .cfg = 0,
  90. },
  91. [LAW_TRGT_IF_PCI_2] = {
  92. .cfg = 0,
  93. },
  94. /* PCI_2 is always host and we dont use iosel to determine enable/disable */
  95. [LAW_TRGT_IF_PCIE_1] = {
  96. .cfg = (1 << 3) | (1 << 4) | (1 << 7),
  97. },
  98. };
  99. #elif defined(CONFIG_MPC8568)
  100. static struct pci_info pci_config_info[] =
  101. {
  102. [LAW_TRGT_IF_PCI] = {
  103. .cfg = 0,
  104. },
  105. [LAW_TRGT_IF_PCIE_1] = {
  106. .cfg = (1 << 3) | (1 << 4) | (1 << 7),
  107. },
  108. };
  109. #elif defined(CONFIG_MPC8569)
  110. static struct pci_info pci_config_info[] =
  111. {
  112. [LAW_TRGT_IF_PCIE_1] = {
  113. .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
  114. (1 << 8) | (1 << 0xc) | (1 << 0xf),
  115. },
  116. };
  117. #elif defined(CONFIG_MPC8572)
  118. static struct pci_info pci_config_info[] =
  119. {
  120. [LAW_TRGT_IF_PCIE_1] = {
  121. .cfg = (1 << 2) | (1 << 3) | (1 << 7) |
  122. (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
  123. },
  124. [LAW_TRGT_IF_PCIE_2] = {
  125. .cfg = (1 << 3) | (1 << 7),
  126. },
  127. [LAW_TRGT_IF_PCIE_3] = {
  128. .cfg = (1 << 7),
  129. },
  130. };
  131. #elif defined(CONFIG_MPC8610)
  132. static struct pci_info pci_config_info[] =
  133. {
  134. [LAW_TRGT_IF_PCI_1] = {
  135. .cfg = 0,
  136. },
  137. [LAW_TRGT_IF_PCIE_1] = {
  138. .cfg = (1 << 1) | (1 << 4),
  139. },
  140. [LAW_TRGT_IF_PCIE_2] = {
  141. .cfg = (1 << 0) | (1 << 4),
  142. },
  143. };
  144. #elif defined(CONFIG_MPC8641)
  145. static struct pci_info pci_config_info[] =
  146. {
  147. [LAW_TRGT_IF_PCIE_1] = {
  148. .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
  149. (1 << 7) | (1 << 0xe) | (1 << 0xf),
  150. },
  151. };
  152. #elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
  153. static struct pci_info pci_config_info[] =
  154. {
  155. [LAW_TRGT_IF_PCIE_1] = {
  156. .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
  157. },
  158. [LAW_TRGT_IF_PCIE_2] = {
  159. .cfg = (1 << 0xe),
  160. },
  161. };
  162. #elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
  163. static struct pci_info pci_config_info[] =
  164. {
  165. [LAW_TRGT_IF_PCIE_1] = {
  166. .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
  167. (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
  168. },
  169. [LAW_TRGT_IF_PCIE_2] = {
  170. .cfg = (1 << 2) | (1 << 0xe),
  171. },
  172. [LAW_TRGT_IF_PCIE_3] = {
  173. .cfg = (1 << 2) | (1 << 4),
  174. },
  175. };
  176. #elif defined(CONFIG_FSL_CORENET)
  177. #else
  178. #error Need to define pci_config_info for processor
  179. #endif
  180. #ifndef CONFIG_FSL_CORENET
  181. int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
  182. {
  183. return ((1 << io_sel) & pci_config_info[trgt].cfg);
  184. }
  185. #endif