ali512x.c 8.7 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * Based on sc520cdp.c from rolo 1.6:
  25. *----------------------------------------------------------------------
  26. * (C) Copyright 2000
  27. * Sysgo Real-Time Solutions GmbH
  28. * Klein-Winternheim, Germany
  29. *----------------------------------------------------------------------
  30. */
  31. #include <config.h>
  32. #include <common.h>
  33. #include <asm/io.h>
  34. #include <ali512x.h>
  35. /* ALI M5123 Logical device numbers:
  36. * 0 FDC
  37. * 1 unused?
  38. * 2 unused?
  39. * 3 lpt
  40. * 4 UART1
  41. * 5 UART2
  42. * 6 RTC
  43. * 7 mouse/kbd
  44. * 8 CIO
  45. */
  46. /*
  47. ************************************************************
  48. * Some access primitives for the ALi chip: *
  49. ************************************************************
  50. */
  51. static void ali_write(u8 index, u8 value)
  52. {
  53. /* write an arbirary register */
  54. outb(index, ALI_INDEX);
  55. outb(value, ALI_DATA);
  56. }
  57. #if 0
  58. static int ali_read(u8 index)
  59. {
  60. outb(index, ALI_INDEX);
  61. return inb(ALI_DATA);
  62. }
  63. #endif
  64. #define ALI_OPEN() \
  65. outb(0x51, ALI_INDEX); \
  66. outb(0x23, ALI_INDEX)
  67. #define ALI_CLOSE() \
  68. outb(0xbb, ALI_INDEX)
  69. /* Select a logical device */
  70. #define ALI_SELDEV(dev) \
  71. ali_write(0x07, dev)
  72. void ali512x_init(void)
  73. {
  74. ALI_OPEN();
  75. ali_write(0x02, 0x01); /* soft reset */
  76. ali_write(0x03, 0x03); /* disable access to CIOs */
  77. ali_write(0x22, 0x00); /* disable direct powerdown */
  78. ali_write(0x23, 0x00); /* disable auto powerdown */
  79. ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
  80. ALI_CLOSE();
  81. }
  82. void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
  83. {
  84. ALI_OPEN();
  85. ALI_SELDEV(0);
  86. ali_write(0x30, enabled?1:0);
  87. if (enabled) {
  88. ali_write(0x60, io >> 8);
  89. ali_write(0x61, io & 0xff);
  90. ali_write(0x70, irq);
  91. ali_write(0x74, dma_channel);
  92. /* AT mode, no drive swap */
  93. ali_write(0xf0, 0x08);
  94. ali_write(0xf1, 0x00);
  95. ali_write(0xf2, 0xff);
  96. ali_write(0xf4, 0x00);
  97. }
  98. ALI_CLOSE();
  99. }
  100. void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
  101. {
  102. ALI_OPEN();
  103. ALI_SELDEV(3);
  104. ali_write(0x30, enabled?1:0);
  105. if (enabled) {
  106. ali_write(0x60, io >> 8);
  107. ali_write(0x61, io & 0xff);
  108. ali_write(0x70, irq);
  109. ali_write(0x74, dma_channel);
  110. /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
  111. ali_write(0xf0, 0xbc);
  112. /* 12 MHz, Burst DMA in ECP */
  113. ali_write(0xf1, 0x05);
  114. }
  115. ALI_CLOSE();
  116. }
  117. void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
  118. {
  119. ALI_OPEN();
  120. ALI_SELDEV(index?5:4);
  121. ali_write(0x30, enabled?1:0);
  122. if (enabled) {
  123. ali_write(0x60, io >> 8);
  124. ali_write(0x61, io & 0xff);
  125. ali_write(0x70, irq);
  126. ali_write(0xf0, 0x00);
  127. ali_write(0xf1, 0x00);
  128. /* huh? write 0xf2 twice - a typo in rolo
  129. * or some secret ali errata? Who knows?
  130. */
  131. if (index) {
  132. ali_write(0xf2, 0x00);
  133. }
  134. ali_write(0xf2, 0x0c);
  135. }
  136. ALI_CLOSE();
  137. }
  138. void ali512x_set_uart2_irda(int enabled)
  139. {
  140. ALI_OPEN();
  141. ALI_SELDEV(5);
  142. ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
  143. ALI_CLOSE();
  144. }
  145. void ali512x_set_rtc(int enabled, u16 io, u8 irq)
  146. {
  147. ALI_OPEN();
  148. ALI_SELDEV(6);
  149. ali_write(0x30, enabled?1:0);
  150. if (enabled) {
  151. ali_write(0x60, io >> 8);
  152. ali_write(0x61, io & 0xff);
  153. ali_write(0x70, irq);
  154. ali_write(0xf0, 0x00);
  155. }
  156. ALI_CLOSE();
  157. }
  158. void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
  159. {
  160. ALI_OPEN();
  161. ALI_SELDEV(7);
  162. ali_write(0x30, enabled?1:0);
  163. if (enabled) {
  164. ali_write(0x70, kbc_irq);
  165. ali_write(0x72, mouse_irq);
  166. ali_write(0xf0, 0x00);
  167. }
  168. ALI_CLOSE();
  169. }
  170. /* Common I/O
  171. *
  172. * (This descripotsion is base on several incompete sources
  173. * since I have not been able to obtain any datasheet for the device
  174. * there may be some mis-understandings burried in here.
  175. * -- Daniel daniel@omicron.se)
  176. *
  177. * There are 22 CIO pins numbered
  178. * 10-17
  179. * 20-25
  180. * 30-37
  181. *
  182. * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
  183. * other functions.
  184. *
  185. * Secondary
  186. * CIO Pin Function Decription
  187. * =======================================================
  188. * CIO10 IRQIN1 Interrupt input 1?
  189. * CIO11 IRQIN2 Interrupt input 2?
  190. * CIO12 IRRX IrDa Receive
  191. * CIO13 IRTX IrDa Transmit
  192. * CIO14 P21 KBC P21 fucntion
  193. * CIO15 P20 KBC P21 fucntion
  194. * CIO16 I2C_CLK I2C Clock
  195. * CIO17 I2C_DAT I2C Data
  196. *
  197. * CIO20 -
  198. * CIO21 -
  199. * CIO22 -
  200. * CIO23 -
  201. * CIO24 -
  202. * CIO25 LOCK Keylock
  203. *
  204. * CIO30 KBC_CLK Keybaord Clock
  205. * CIO31 CS0J General Chip Select decoder CS0J
  206. * CIO32 CS1J General Chip Select decoder CS1J
  207. * CIO33 ALT_KCLK Alternative Keyboard Clock
  208. * CIO34 ALT_KDAT Alternative Keyboard Data
  209. * CIO35 ALT_MCLK Alternative Mouse Clock
  210. * CIO36 ALT_MDAT Alternative Mouse Data
  211. * CIO37 ALT_KBC Alternative KBC select
  212. *
  213. * The CIO use an indirect address scheme.
  214. *
  215. * Reigster 3 in the SIO is used to select the index and data
  216. * port addresses where the CIO I/O registers show up.
  217. * The function selection registers are accessible under
  218. * function SIO 8.
  219. *
  220. * SIO reigster 3 (CIO Address Selection) bit definitions:
  221. * bit 7 CIO index and data registers enabled
  222. * bit 1-0 CIO indirect registers port address select
  223. * 0 index = 0xE0 data = 0xE1
  224. * 1 index = 0xE2 data = 0xE3
  225. * 2 index = 0xE4 data = 0xE5
  226. * 3 index = 0xEA data = 0xEB
  227. *
  228. * There are three CIO I/O register accessed via CIO index port and CIO data port
  229. * 0x01 CIO 10-17 data
  230. * 0x02 CIO 20-25 data (bits 7-6 unused)
  231. * 0x03 CIO 30-37 data
  232. *
  233. *
  234. * The pin function is accessed through normal
  235. * SIO registers, each register have the same format:
  236. *
  237. * Bit Function Value
  238. * 0 Input/output 1=input
  239. * 1 Polarity of signal 1=inverted
  240. * 2 Unused ??
  241. * 3 Function (normal or special) 1=special
  242. * 7-4 Unused
  243. *
  244. * SIO REG
  245. * 0xe0 CIO 10 Config
  246. * 0xe1 CIO 11 Config
  247. * 0xe2 CIO 12 Config
  248. * 0xe3 CIO 13 Config
  249. * 0xe4 CIO 14 Config
  250. * 0xe5 CIO 15 Config
  251. * 0xe6 CIO 16 Config
  252. * 0xe7 CIO 16 Config
  253. *
  254. * 0xe8 CIO 20 Config
  255. * 0xe9 CIO 21 Config
  256. * 0xea CIO 22 Config
  257. * 0xeb CIO 23 Config
  258. * 0xec CIO 24 Config
  259. * 0xed CIO 25 Config
  260. *
  261. * 0xf5 CIO 30 Config
  262. * 0xf6 CIO 31 Config
  263. * 0xf7 CIO 32 Config
  264. * 0xf8 CIO 33 Config
  265. * 0xf9 CIO 34 Config
  266. * 0xfa CIO 35 Config
  267. * 0xfb CIO 36 Config
  268. * 0xfc CIO 37 Config
  269. *
  270. */
  271. #define ALI_CIO_PORT_SEL 0x83
  272. #define ALI_CIO_INDEX 0xea
  273. #define ALI_CIO_DATA 0xeb
  274. void ali512x_set_cio(int enabled)
  275. {
  276. int i;
  277. ALI_OPEN();
  278. if (enabled) {
  279. ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */
  280. } else {
  281. ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
  282. }
  283. ALI_SELDEV(8);
  284. ali_write(0x30, enabled?1:0);
  285. /* set all pins to input to start with */
  286. for (i=0xe0;i<0xee;i++) {
  287. ali_write(i, 1);
  288. }
  289. for (i=0xf5;i<0xfe;i++) {
  290. ali_write(i, 1);
  291. }
  292. ALI_CLOSE();
  293. }
  294. void ali512x_cio_function(int pin, int special, int inv, int input)
  295. {
  296. u8 data;
  297. u8 addr;
  298. /* valid pins are 10-17, 20-25 and 30-37 */
  299. if (pin >= 10 && pin <= 17) {
  300. addr = 0xe0+(pin&7);
  301. } else if (pin >= 20 && pin <= 25) {
  302. addr = 0xe8+(pin&7);
  303. } else if (pin >= 30 && pin <= 37) {
  304. addr = 0xf5+(pin&7);
  305. } else {
  306. return;
  307. }
  308. ALI_OPEN();
  309. ALI_SELDEV(8);
  310. data=0xf4;
  311. if (special) {
  312. data |= 0x08;
  313. } else {
  314. if (inv) {
  315. data |= 0x02;
  316. }
  317. if (input) {
  318. data |= 0x01;
  319. }
  320. }
  321. ali_write(addr, data);
  322. ALI_CLOSE();
  323. }
  324. void ali512x_cio_out(int pin, int value)
  325. {
  326. u8 reg;
  327. u8 data;
  328. u8 bit;
  329. reg = pin/10;
  330. bit = 1 << (pin%10);
  331. outb(reg, ALI_CIO_INDEX); /* select I/O register */
  332. data = inb(ALI_CIO_DATA);
  333. if (value) {
  334. data |= bit;
  335. } else {
  336. data &= ~bit;
  337. }
  338. outb(data, ALI_CIO_DATA);
  339. }
  340. int ali512x_cio_in(int pin)
  341. {
  342. u8 reg;
  343. u8 data;
  344. u8 bit;
  345. /* valid pins are 10-17, 20-25 and 30-37 */
  346. reg = pin/10;
  347. bit = 1 << (pin%10);
  348. outb(reg, ALI_CIO_INDEX); /* select I/O register */
  349. data = inb(ALI_CIO_DATA);
  350. return data & bit;
  351. }