M5329EVB.h 7.3 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF5329 FireEngine board.
  3. *
  4. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * board/config.h - configuration options, board specific
  27. */
  28. #ifndef _M5329EVB_H
  29. #define _M5329EVB_H
  30. /*
  31. * High Level Configuration Options
  32. * (easy to change)
  33. */
  34. #define CONFIG_MCF532x /* define processor family */
  35. #define CONFIG_M5329 /* define processor type */
  36. #undef DEBUG
  37. #define CONFIG_MCFUART
  38. #define CFG_UART_PORT (0)
  39. #define CONFIG_BAUDRATE 115200
  40. #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  41. #undef CONFIG_WATCHDOG
  42. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  43. #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  44. CFG_CMD_CACHE | \
  45. CFG_CMD_DATE | \
  46. CFG_CMD_ELF | \
  47. CFG_CMD_FLASH | \
  48. CFG_CMD_I2C | \
  49. (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
  50. CFG_CMD_MEMORY | \
  51. CFG_CMD_MISC | \
  52. CFG_CMD_MII | \
  53. CFG_CMD_NET | \
  54. CFG_CMD_PING | \
  55. CFG_CMD_REGINFO \
  56. )
  57. #define CFG_UNIFY_CACHE
  58. #define CONFIG_MCFFEC
  59. #ifdef CONFIG_MCFFEC
  60. # define CONFIG_NET_MULTI 1
  61. # define CONFIG_MII 1
  62. # define CFG_DISCOVER_PHY
  63. # define CFG_RX_ETH_BUFFER 8
  64. # define CFG_FAULT_ECHO_LINK_DOWN
  65. # define CFG_FEC0_PINMUX 0
  66. # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
  67. # define MCFFEC_TOUT_LOOP 50000
  68. /* If CFG_DISCOVER_PHY is not defined - hardcoded */
  69. # ifndef CFG_DISCOVER_PHY
  70. # define FECDUPLEX FULL
  71. # define FECSPEED _100BASET
  72. # else
  73. # ifndef CFG_FAULT_ECHO_LINK_DOWN
  74. # define CFG_FAULT_ECHO_LINK_DOWN
  75. # endif
  76. # endif /* CFG_DISCOVER_PHY */
  77. #endif
  78. #define CONFIG_MCFRTC
  79. #undef RTC_DEBUG
  80. /* Timer */
  81. #define CONFIG_MCFTMR
  82. #undef CONFIG_MCFPIT
  83. /* I2C */
  84. #define CONFIG_FSL_I2C
  85. #define CONFIG_HARD_I2C /* I2C with hw support */
  86. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  87. #define CFG_I2C_SPEED 80000
  88. #define CFG_I2C_SLAVE 0x7F
  89. #define CFG_I2C_OFFSET 0x58000
  90. #define CFG_IMMR CFG_MBAR
  91. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  92. #include <cmd_confdefs.h>
  93. #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
  94. #ifdef CONFIG_MCFFEC
  95. # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
  96. # define CONFIG_IPADDR 192.162.1.2
  97. # define CONFIG_NETMASK 255.255.255.0
  98. # define CONFIG_SERVERIP 192.162.1.1
  99. # define CONFIG_GATEWAYIP 192.162.1.1
  100. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  101. #endif /* FEC_ENET */
  102. #define CONFIG_HOSTNAME M5329EVB
  103. #define CONFIG_EXTRA_ENV_SETTINGS \
  104. "netdev=eth0\0" \
  105. "loadaddr=40010000\0" \
  106. "u-boot=u-boot.bin\0" \
  107. "load=tftp ${loadaddr) ${u-boot}\0" \
  108. "upd=run load; run prog\0" \
  109. "prog=prot off 0 2ffff;" \
  110. "era 0 2ffff;" \
  111. "cp.b ${loadaddr} 0 ${filesize};" \
  112. "save\0" \
  113. ""
  114. #define CONFIG_PRAM 512 /* 512 KB */
  115. #define CFG_PROMPT "-> "
  116. #define CFG_LONGHELP /* undef to save memory */
  117. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  118. # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  119. #else
  120. # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  121. #endif
  122. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  123. #define CFG_MAXARGS 16 /* max number of command args */
  124. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  125. #define CFG_LOAD_ADDR 0x40010000
  126. #define CFG_HZ 1000
  127. #define CFG_CLK 80000000
  128. #define CFG_CPU_CLK CFG_CLK * 3
  129. #define CFG_MBAR 0xFC000000
  130. /*
  131. * Low Level Configuration Settings
  132. * (address mappings, register initial values, etc.)
  133. * You should know what you are doing if you make changes here.
  134. */
  135. /*-----------------------------------------------------------------------
  136. * Definitions for initial stack pointer and data area (in DPRAM)
  137. */
  138. #define CFG_INIT_RAM_ADDR 0x80000000
  139. #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
  140. #define CFG_INIT_RAM_CTRL 0x221
  141. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  142. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  143. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  144. /*-----------------------------------------------------------------------
  145. * Start addresses for the final memory configuration
  146. * (Set up by the startup code)
  147. * Please note that CFG_SDRAM_BASE _must_ start at 0
  148. */
  149. #define CFG_SDRAM_BASE 0x40000000
  150. #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
  151. #define CFG_SDRAM_CFG1 0x53722730
  152. #define CFG_SDRAM_CFG2 0x56670000
  153. #define CFG_SDRAM_CTRL 0xE1092000
  154. #define CFG_SDRAM_EMOD 0x40010000
  155. #define CFG_SDRAM_MODE 0x018D0000
  156. #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
  157. #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
  158. #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
  159. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  160. #define CFG_BOOTPARAMS_LEN 64*1024
  161. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  162. /*
  163. * For booting Linux, the board info and command line data
  164. * have to be in the first 8 MB of memory, since this is
  165. * the maximum mapped by the Linux kernel during initialization ??
  166. */
  167. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  168. /*-----------------------------------------------------------------------
  169. * FLASH organization
  170. */
  171. #define CFG_FLASH_CFI
  172. #ifdef CFG_FLASH_CFI
  173. # define CFG_FLASH_CFI_DRIVER 1
  174. # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
  175. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  176. # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  177. # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  178. # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  179. #endif
  180. #define CFG_FLASH_BASE 0
  181. #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
  182. /* Configuration for environment
  183. * Environment is embedded in u-boot in the second sector of the flash
  184. */
  185. #define CFG_ENV_OFFSET 0x4000
  186. #define CFG_ENV_SECT_SIZE 0x2000
  187. #define CFG_ENV_IS_IN_FLASH 1
  188. #define CFG_ENV_IS_EMBEDDED 1
  189. /*-----------------------------------------------------------------------
  190. * Cache Configuration
  191. */
  192. #define CFG_CACHELINE_SIZE 16
  193. /*-----------------------------------------------------------------------
  194. * Chipselect bank definitions
  195. */
  196. /*
  197. * CS0 - NOR Flash 1, 2, 4, or 8MB
  198. * CS1 - CompactFlash and registers
  199. * CS2 - NAND Flash 16, 32, or 64MB
  200. * CS3 - Available
  201. * CS4 - Available
  202. * CS5 - Available
  203. */
  204. #define CFG_CS0_BASE 0
  205. #define CFG_CS0_MASK 0x007f0001
  206. #define CFG_CS0_CTRL 0x00001fa0
  207. #define CFG_CS1_BASE 0x1000
  208. #define CFG_CS1_MASK 0x001f0001
  209. #define CFG_CS1_CTRL 0x002A3780
  210. #ifdef NANDFLASH_SIZE
  211. #define CFG_CS2_BASE 0x00800000
  212. #define CFG_CS2_MASK 0x00ff0001
  213. #define CFG_CS2_CTRL 0x00001f60
  214. #endif
  215. #define CONFIG_UDP_CHECKSUM
  216. #endif /* _M5329EVB_H */