ehci-faraday.c 3.5 KB

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  1. /*
  2. * Faraday USB 2.0 EHCI Controller
  3. *
  4. * (C) Copyright 2010 Faraday Technology
  5. * Dante Su <dantesu@faraday-tech.com>
  6. *
  7. * This file is released under the terms of GPL v2 and any later version.
  8. * See the file COPYING in the root directory of the source tree for details.
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <usb.h>
  13. #include <usb/fusbh200.h>
  14. #include <usb/fotg210.h>
  15. #include "ehci.h"
  16. #ifndef CONFIG_USB_EHCI_BASE_LIST
  17. #define CONFIG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
  18. #endif
  19. union ehci_faraday_regs {
  20. struct fusbh200_regs usb;
  21. struct fotg210_regs otg;
  22. };
  23. static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs)
  24. {
  25. return !readl(&regs->usb.easstr);
  26. }
  27. /*
  28. * Create the appropriate control structures to manage
  29. * a new EHCI host controller.
  30. */
  31. int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
  32. struct ehci_hcor **ret_hcor)
  33. {
  34. struct ehci_hccr *hccr;
  35. struct ehci_hcor *hcor;
  36. union ehci_faraday_regs *regs;
  37. uint32_t base_list[] = CONFIG_USB_EHCI_BASE_LIST;
  38. if (index < 0 || index >= ARRAY_SIZE(base_list))
  39. return -1;
  40. regs = (void __iomem *)base_list[index];
  41. hccr = (struct ehci_hccr *)&regs->usb.hccr;
  42. hcor = (struct ehci_hcor *)&regs->usb.hcor;
  43. if (ehci_is_fotg2xx(regs)) {
  44. /* A-device bus reset */
  45. /* ... Power off A-device */
  46. setbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSDROP);
  47. /* ... Drop vbus and bus traffic */
  48. clrbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSREQ);
  49. mdelay(1);
  50. /* ... Power on A-device */
  51. clrbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSDROP);
  52. /* ... Drive vbus and bus traffic */
  53. setbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSREQ);
  54. mdelay(1);
  55. /* Disable OTG & DEV interrupts, triggered at level-high */
  56. writel(IMR_IRQLH | IMR_OTG | IMR_DEV, &regs->otg.imr);
  57. /* Clear all interrupt status */
  58. writel(ISR_HOST | ISR_OTG | ISR_DEV, &regs->otg.isr);
  59. } else {
  60. /* Interrupt=level-high */
  61. setbits_le32(&regs->usb.bmcsr, BMCSR_IRQLH);
  62. /* VBUS on */
  63. clrbits_le32(&regs->usb.bmcsr, BMCSR_VBUS_OFF);
  64. /* Disable all interrupts */
  65. writel(0x00, &regs->usb.bmier);
  66. writel(0x1f, &regs->usb.bmisr);
  67. }
  68. *ret_hccr = hccr;
  69. *ret_hcor = hcor;
  70. return 0;
  71. }
  72. /*
  73. * Destroy the appropriate control structures corresponding
  74. * the the EHCI host controller.
  75. */
  76. int ehci_hcd_stop(int index)
  77. {
  78. return 0;
  79. }
  80. /*
  81. * This ehci_set_usbmode() overrides the weak function
  82. * in "ehci-hcd.c".
  83. */
  84. void ehci_set_usbmode(int index)
  85. {
  86. /* nothing needs to be done */
  87. }
  88. /*
  89. * This ehci_get_port_speed() overrides the weak function
  90. * in "ehci-hcd.c".
  91. */
  92. int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
  93. {
  94. int spd, ret = PORTSC_PSPD_HS;
  95. union ehci_faraday_regs *regs = (void __iomem *)((ulong)hcor - 0x10);
  96. if (ehci_is_fotg2xx(regs))
  97. spd = OTGCSR_SPD(readl(&regs->otg.otgcsr));
  98. else
  99. spd = BMCSR_SPD(readl(&regs->usb.bmcsr));
  100. switch (spd) {
  101. case 0: /* full speed */
  102. ret = PORTSC_PSPD_FS;
  103. break;
  104. case 1: /* low speed */
  105. ret = PORTSC_PSPD_LS;
  106. break;
  107. case 2: /* high speed */
  108. ret = PORTSC_PSPD_HS;
  109. break;
  110. default:
  111. printf("ehci-faraday: invalid device speed\n");
  112. break;
  113. }
  114. return ret;
  115. }
  116. /*
  117. * This ehci_get_portsc_register() overrides the weak function
  118. * in "ehci-hcd.c".
  119. */
  120. uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
  121. {
  122. /* Faraday EHCI has one and only one portsc register */
  123. if (port) {
  124. /* Printing the message would cause a scan failure! */
  125. debug("The request port(%d) is not configured\n", port);
  126. return NULL;
  127. }
  128. /* Faraday EHCI PORTSC register offset is 0x20 from hcor */
  129. return (uint32_t *)((uint8_t *)hcor + 0x20);
  130. }