clk.c 2.0 KB

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  1. /*
  2. * Copyright (C) 2005-2008 Atmel Corporation
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/clk.h>
  25. #include <asm/arch/memory-map.h>
  26. #include "sm.h"
  27. void clk_init(void)
  28. {
  29. uint32_t cksel;
  30. /* in case of soft resets, disable watchdog */
  31. sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
  32. sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
  33. #ifdef CONFIG_PLL
  34. /* Initialize the PLL */
  35. sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
  36. | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
  37. | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
  38. | SM_BF(PLLOPT, CFG_PLL0_OPT)
  39. | SM_BF(PLLOSC, 0)
  40. | SM_BIT(PLLEN)));
  41. /* Wait for lock */
  42. while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
  43. #endif
  44. /* Set up clocks for the CPU and all peripheral buses */
  45. cksel = 0;
  46. if (CFG_CLKDIV_CPU)
  47. cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
  48. if (CFG_CLKDIV_HSB)
  49. cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
  50. if (CFG_CLKDIV_PBA)
  51. cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
  52. if (CFG_CLKDIV_PBB)
  53. cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
  54. sm_writel(PM_CKSEL, cksel);
  55. #ifdef CONFIG_PLL
  56. /* Use PLL0 as main clock */
  57. sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
  58. #endif
  59. }