atstk1000.c 2.7 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <asm/sdram.h>
  25. #include <asm/arch/clk.h>
  26. #include <asm/arch/gpio.h>
  27. #include <asm/arch/hmatrix.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. static const struct sdram_config sdram_config = {
  30. #if defined(CONFIG_ATSTK1006)
  31. /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
  32. .data_bits = SDRAM_DATA_32BIT,
  33. .row_bits = 13,
  34. .col_bits = 9,
  35. .bank_bits = 2,
  36. .cas = 2,
  37. .twr = 2,
  38. .trc = 7,
  39. .trp = 2,
  40. .trcd = 2,
  41. .tras = 4,
  42. .txsr = 7,
  43. /* 7.81 us */
  44. .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  45. #else
  46. /* MT48LC2M32B2P-5 (8 MB) on motherboard */
  47. #ifdef CONFIG_ATSTK1004
  48. .data_bits = SDRAM_DATA_16BIT,
  49. #else
  50. .data_bits = SDRAM_DATA_32BIT,
  51. #endif
  52. #ifdef CONFIG_ATSTK1000_16MB_SDRAM
  53. /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
  54. .row_bits = 12,
  55. #else
  56. .row_bits = 11,
  57. #endif
  58. .col_bits = 8,
  59. .bank_bits = 2,
  60. .cas = 3,
  61. .twr = 2,
  62. .trc = 7,
  63. .trp = 2,
  64. .trcd = 2,
  65. .tras = 5,
  66. .txsr = 5,
  67. /* 15.6 us */
  68. .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
  69. #endif
  70. };
  71. int board_early_init_f(void)
  72. {
  73. /* Enable SDRAM in the EBI mux */
  74. hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  75. gpio_enable_ebi();
  76. gpio_enable_usart1();
  77. #if defined(CONFIG_MACB)
  78. gpio_enable_macb0();
  79. gpio_enable_macb1();
  80. #endif
  81. #if defined(CONFIG_MMC)
  82. gpio_enable_mmci();
  83. #endif
  84. return 0;
  85. }
  86. long int initdram(int board_type)
  87. {
  88. unsigned long expected_size;
  89. unsigned long actual_size;
  90. void *sdram_base;
  91. sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
  92. expected_size = sdram_init(sdram_base, &sdram_config);
  93. actual_size = get_ram_size(sdram_base, expected_size);
  94. unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
  95. if (expected_size != actual_size)
  96. printf("Warning: Only %u of %u MiB SDRAM is working\n",
  97. actual_size >> 20, expected_size >> 20);
  98. return actual_size;
  99. }
  100. void board_init_info(void)
  101. {
  102. gd->bd->bi_phy_id[0] = 0x10;
  103. gd->bd->bi_phy_id[1] = 0x11;
  104. }