cpu.c 2.0 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <asm/mipsregs.h>
  26. #include <asm/cacheops.h>
  27. #include <asm/reboot.h>
  28. #define cache_op(op,addr) \
  29. __asm__ __volatile__( \
  30. " .set push \n" \
  31. " .set noreorder \n" \
  32. " .set mips3\n\t \n" \
  33. " cache %0, %1 \n" \
  34. " .set pop \n" \
  35. : \
  36. : "i" (op), "R" (*(unsigned char *)(addr)))
  37. void __attribute__((weak)) _machine_restart(void)
  38. {
  39. }
  40. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  41. {
  42. _machine_restart();
  43. fprintf(stderr, "*** reset failed ***\n");
  44. return 0;
  45. }
  46. void flush_cache(ulong start_addr, ulong size)
  47. {
  48. unsigned long lsize = CFG_CACHELINE_SIZE;
  49. unsigned long addr = start_addr & ~(lsize - 1);
  50. unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
  51. while (1) {
  52. cache_op(Hit_Writeback_Inv_D, addr);
  53. cache_op(Hit_Invalidate_I, addr);
  54. if (addr == aend)
  55. break;
  56. addr += lsize;
  57. }
  58. }
  59. void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
  60. {
  61. write_c0_entrylo0(low0);
  62. write_c0_pagemask(pagemask);
  63. write_c0_entrylo1(low1);
  64. write_c0_entryhi(hi);
  65. write_c0_index(index);
  66. tlb_write_indexed();
  67. }