tegra20-tec.dts 1.5 KB

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  1. /dts-v1/;
  2. /include/ ARCH_CPU_DTS
  3. / {
  4. model = "Avionic Design Tamonten Evaluation Carrier";
  5. compatible = "ad,tec", "nvidia,tegra20";
  6. aliases {
  7. usb0 = "/usb@c5008000";
  8. };
  9. memory {
  10. reg = <0x00000000 0x20000000>;
  11. };
  12. clocks {
  13. clk_32k: clk_32k {
  14. clock-frequency = <32000>;
  15. };
  16. osc {
  17. clock-frequency = <12000000>;
  18. };
  19. };
  20. host1x {
  21. status = "okay";
  22. dc@54200000 {
  23. status = "okay";
  24. rgb {
  25. nvidia,panel = <&lcd_panel>;
  26. status = "okay";
  27. };
  28. };
  29. };
  30. clock@60006000 {
  31. clocks = <&clk_32k &osc>;
  32. };
  33. serial@70006300 {
  34. clock-frequency = <216000000>;
  35. };
  36. i2c@7000c000 {
  37. status = "disabled";
  38. };
  39. i2c@7000c400 {
  40. status = "disabled";
  41. };
  42. i2c@7000c500 {
  43. status = "disabled";
  44. };
  45. i2c@7000d000 {
  46. status = "disabled";
  47. };
  48. usb@c5000000 {
  49. status = "disabled";
  50. };
  51. usb@c5004000 {
  52. status = "disabled";
  53. };
  54. nand-controller@70008000 {
  55. nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
  56. nvidia,width = <8>;
  57. nvidia,timing = <26 100 20 80 20 10 12 10 70>;
  58. nand@0 {
  59. reg = <0>;
  60. compatible = "hynix,hy27uf4g2b", "nand-flash";
  61. };
  62. };
  63. lcd_panel: panel {
  64. clock = <33260000>;
  65. xres = <800>;
  66. yres = <480>;
  67. left-margin = <120>;
  68. right-margin = <120>;
  69. hsync-len = <16>;
  70. lower-margin = <15>;
  71. upper-margin = <15>;
  72. vsync-len = <15>;
  73. nvidia,bits-per-pixel = <16>;
  74. nvidia,pwm = <&pwm 0 500000>;
  75. nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
  76. nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
  77. nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
  78. nvidia,panel-timings = <0 0 0 0>;
  79. };
  80. };