pci_sh4.c 2.5 KB

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  1. /*
  2. * SH4 PCI Controller (PCIC) for U-Boot.
  3. * (C) Dustin McIntire (dustin@sensoria.com)
  4. * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  5. * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
  6. *
  7. * u-boot/cpu/sh4/pci-sh4.c
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <asm/processor.h>
  29. #include <asm/io.h>
  30. #include <asm/pci.h>
  31. #include <pci.h>
  32. int pci_sh4_init(struct pci_controller *hose)
  33. {
  34. hose->first_busno = 0;
  35. hose->region_count = 0;
  36. hose->last_busno = 0xff;
  37. /* PCI memory space */
  38. pci_set_region(hose->regions + 0,
  39. CONFIG_PCI_MEM_BUS,
  40. CONFIG_PCI_MEM_PHYS,
  41. CONFIG_PCI_MEM_SIZE,
  42. PCI_REGION_MEM);
  43. hose->region_count++;
  44. /* PCI IO space */
  45. pci_set_region(hose->regions + 1,
  46. CONFIG_PCI_IO_BUS,
  47. CONFIG_PCI_IO_PHYS,
  48. CONFIG_PCI_IO_SIZE,
  49. PCI_REGION_IO);
  50. hose->region_count++;
  51. #if defined(CONFIG_PCI_SYS_BUS)
  52. /* PCI System Memory space */
  53. pci_set_region(hose->regions + 2,
  54. CONFIG_PCI_SYS_BUS,
  55. CONFIG_PCI_SYS_PHYS,
  56. CONFIG_PCI_SYS_SIZE,
  57. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  58. hose->region_count++;
  59. #endif
  60. udelay(1000);
  61. pci_set_ops(hose,
  62. pci_hose_read_config_byte_via_dword,
  63. pci_hose_read_config_word_via_dword,
  64. pci_sh4_read_config_dword,
  65. pci_hose_write_config_byte_via_dword,
  66. pci_hose_write_config_word_via_dword,
  67. pci_sh4_write_config_dword);
  68. pci_register_hose(hose);
  69. udelay(1000);
  70. #ifdef CONFIG_PCI_SCAN_SHOW
  71. printf("PCI: Bus Dev VenId DevId Class Int\n");
  72. #endif
  73. hose->last_busno = pci_hose_scan(hose);
  74. return 0;
  75. }
  76. int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
  77. {
  78. return 0;
  79. }
  80. #ifdef CONFIG_PCI_SCAN_SHOW
  81. int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
  82. {
  83. return 1;
  84. }
  85. #endif /* CONFIG_PCI_SCAN_SHOW */