sh7785lcr.c 2.1 KB

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  1. /*
  2. * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. */
  19. #include <common.h>
  20. #include <asm/io.h>
  21. #include <asm/processor.h>
  22. #include <asm/pci.h>
  23. #include <netdev.h>
  24. int checkboard(void)
  25. {
  26. puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
  27. return 0;
  28. }
  29. int board_init(void)
  30. {
  31. return 0;
  32. }
  33. int dram_init(void)
  34. {
  35. DECLARE_GLOBAL_DATA_PTR;
  36. gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
  37. gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  38. printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
  39. return 0;
  40. }
  41. static struct pci_controller hose;
  42. void pci_init_board(void)
  43. {
  44. pci_sh7780_init(&hose);
  45. }
  46. int board_eth_init(bd_t *bis)
  47. {
  48. return pci_eth_init(bis);
  49. }
  50. #if defined(CONFIG_SH_32BIT)
  51. int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  52. {
  53. /* clear ITLB */
  54. writel(0x00000004, 0xff000010);
  55. /* delete PMB for peripheral */
  56. writel(0, PMB_ADDR_BASE(0));
  57. writel(0, PMB_DATA_BASE(0));
  58. writel(0, PMB_ADDR_BASE(1));
  59. writel(0, PMB_DATA_BASE(1));
  60. writel(0, PMB_ADDR_BASE(2));
  61. writel(0, PMB_DATA_BASE(2));
  62. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  63. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
  64. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
  65. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
  66. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
  67. return 0;
  68. }
  69. U_BOOT_CMD(
  70. pmb, 1, 1, do_pmb,
  71. "pmb - PMB setting\n",
  72. "\n"
  73. " - PMB setting for all SDRAM mapping\n"
  74. );
  75. #endif