da850evm.c 8.4 KB

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  1. /*
  2. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * Based on da830evm.c. Original Copyrights follow:
  5. *
  6. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <common.h>
  24. #include <i2c.h>
  25. #include <net.h>
  26. #include <netdev.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/emif_defs.h>
  29. #include <asm/arch/emac_defs.h>
  30. #include <asm/io.h>
  31. #include <asm/arch/davinci_misc.h>
  32. #include <asm/arch/da8xx_common.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  35. /* SPI0 pin muxer settings */
  36. static const struct pinmux_config spi1_pins[] = {
  37. { pinmux(5), 1, 1 },
  38. { pinmux(5), 1, 2 },
  39. { pinmux(5), 1, 4 },
  40. { pinmux(5), 1, 5 }
  41. };
  42. /* UART pin muxer settings */
  43. static const struct pinmux_config uart_pins[] = {
  44. { pinmux(0), 4, 6 },
  45. { pinmux(0), 4, 7 },
  46. { pinmux(4), 2, 4 },
  47. { pinmux(4), 2, 5 }
  48. };
  49. #ifdef CONFIG_DRIVER_TI_EMAC
  50. static const struct pinmux_config emac_pins[] = {
  51. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  52. { pinmux(14), 8, 2 },
  53. { pinmux(14), 8, 3 },
  54. { pinmux(14), 8, 4 },
  55. { pinmux(14), 8, 5 },
  56. { pinmux(14), 8, 6 },
  57. { pinmux(14), 8, 7 },
  58. { pinmux(15), 8, 1 },
  59. #else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
  60. { pinmux(2), 8, 1 },
  61. { pinmux(2), 8, 2 },
  62. { pinmux(2), 8, 3 },
  63. { pinmux(2), 8, 4 },
  64. { pinmux(2), 8, 5 },
  65. { pinmux(2), 8, 6 },
  66. { pinmux(2), 8, 7 },
  67. { pinmux(3), 8, 0 },
  68. { pinmux(3), 8, 1 },
  69. { pinmux(3), 8, 2 },
  70. { pinmux(3), 8, 3 },
  71. { pinmux(3), 8, 4 },
  72. { pinmux(3), 8, 5 },
  73. { pinmux(3), 8, 6 },
  74. { pinmux(3), 8, 7 },
  75. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  76. { pinmux(4), 8, 0 },
  77. { pinmux(4), 8, 1 }
  78. };
  79. /* I2C pin muxer settings */
  80. static const struct pinmux_config i2c_pins[] = {
  81. { pinmux(4), 2, 2 },
  82. { pinmux(4), 2, 3 }
  83. };
  84. #ifdef CONFIG_NAND_DAVINCI
  85. const struct pinmux_config nand_pins[] = {
  86. { pinmux(7), 1, 1 },
  87. { pinmux(7), 1, 2 },
  88. { pinmux(7), 1, 4 },
  89. { pinmux(7), 1, 5 },
  90. { pinmux(9), 1, 0 },
  91. { pinmux(9), 1, 1 },
  92. { pinmux(9), 1, 2 },
  93. { pinmux(9), 1, 3 },
  94. { pinmux(9), 1, 4 },
  95. { pinmux(9), 1, 5 },
  96. { pinmux(9), 1, 6 },
  97. { pinmux(9), 1, 7 },
  98. { pinmux(12), 1, 5 },
  99. { pinmux(12), 1, 6 }
  100. };
  101. #endif
  102. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  103. #define HAS_RMII 1
  104. #else
  105. #define HAS_RMII 0
  106. #endif
  107. #endif /* CONFIG_DRIVER_TI_EMAC */
  108. static const struct pinmux_resource pinmuxes[] = {
  109. #ifdef CONFIG_SPI_FLASH
  110. PINMUX_ITEM(spi1_pins),
  111. #endif
  112. PINMUX_ITEM(uart_pins),
  113. PINMUX_ITEM(i2c_pins),
  114. #ifdef CONFIG_NAND_DAVINCI
  115. PINMUX_ITEM(nand_pins),
  116. #endif
  117. };
  118. static const struct lpsc_resource lpsc[] = {
  119. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  120. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  121. { DAVINCI_LPSC_EMAC }, /* image download */
  122. { DAVINCI_LPSC_UART2 }, /* console */
  123. { DAVINCI_LPSC_GPIO },
  124. };
  125. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  126. #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
  127. #endif
  128. /*
  129. * get_board_rev() - setup to pass kernel board revision information
  130. * Returns:
  131. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  132. * 0000b - 300 MHz
  133. * 0001b - 372 MHz
  134. * 0010b - 408 MHz
  135. * 0011b - 456 MHz
  136. */
  137. u32 get_board_rev(void)
  138. {
  139. char *s;
  140. u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
  141. u32 rev = 0;
  142. s = getenv("maxcpuclk");
  143. if (s)
  144. maxcpuclk = simple_strtoul(s, NULL, 10);
  145. if (maxcpuclk >= 456000000)
  146. rev = 3;
  147. else if (maxcpuclk >= 408000000)
  148. rev = 2;
  149. else if (maxcpuclk >= 372000000)
  150. rev = 1;
  151. return rev;
  152. }
  153. int board_init(void)
  154. {
  155. #ifndef CONFIG_USE_IRQ
  156. irq_init();
  157. #endif
  158. #ifdef CONFIG_NAND_DAVINCI
  159. /*
  160. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  161. * Linux kernel @ 25MHz EMIFA
  162. */
  163. writel((DAVINCI_ABCR_WSETUP(0) |
  164. DAVINCI_ABCR_WSTROBE(0) |
  165. DAVINCI_ABCR_WHOLD(0) |
  166. DAVINCI_ABCR_RSETUP(0) |
  167. DAVINCI_ABCR_RSTROBE(1) |
  168. DAVINCI_ABCR_RHOLD(0) |
  169. DAVINCI_ABCR_TA(0) |
  170. DAVINCI_ABCR_ASIZE_8BIT),
  171. &davinci_emif_regs->ab2cr); /* CS3 */
  172. #endif
  173. /* arch number of the board */
  174. gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
  175. /* address of boot parameters */
  176. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  177. /*
  178. * Power on required peripherals
  179. * ARM does not have access by default to PSC0 and PSC1
  180. * assuming here that the DSP bootloader has set the IOPU
  181. * such that PSC access is available to ARM
  182. */
  183. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  184. return 1;
  185. /* setup the SUSPSRC for ARM to control emulation suspend */
  186. writel(readl(&davinci_syscfg_regs->suspsrc) &
  187. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  188. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  189. DAVINCI_SYSCFG_SUSPSRC_UART2),
  190. &davinci_syscfg_regs->suspsrc);
  191. /* configure pinmux settings */
  192. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  193. return 1;
  194. #ifdef CONFIG_DRIVER_TI_EMAC
  195. if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
  196. return 1;
  197. da850_emac_mii_mode_sel(HAS_RMII);
  198. #endif /* CONFIG_DRIVER_TI_EMAC */
  199. /* enable the console UART */
  200. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  201. DAVINCI_UART_PWREMU_MGMT_UTRST),
  202. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  203. return 0;
  204. }
  205. #ifdef CONFIG_DRIVER_TI_EMAC
  206. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  207. /**
  208. * rmii_hw_init
  209. *
  210. * DA850/OMAP-L138 EVM can interface to a daughter card for
  211. * additional features. This card has an I2C GPIO Expander TCA6416
  212. * to select the required functions like camera, RMII Ethernet,
  213. * character LCD, video.
  214. *
  215. * Initialization of the expander involves configuring the
  216. * polarity and direction of the ports. P07-P05 are used here.
  217. * These ports are connected to a Mux chip which enables only one
  218. * functionality at a time.
  219. *
  220. * For RMII phy to respond, the MII MDIO clock has to be disabled
  221. * since both the PHY devices have address as zero. The MII MDIO
  222. * clock is controlled via GPIO2[6].
  223. *
  224. * This code is valid for Beta version of the hardware
  225. */
  226. int rmii_hw_init(void)
  227. {
  228. const struct pinmux_config gpio_pins[] = {
  229. { pinmux(6), 8, 1 }
  230. };
  231. u_int8_t buf[2];
  232. unsigned int temp;
  233. int ret;
  234. /* PinMux for GPIO */
  235. if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
  236. return 1;
  237. /* I2C Exapnder configuration */
  238. /* Set polarity to non-inverted */
  239. buf[0] = 0x0;
  240. buf[1] = 0x0;
  241. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
  242. if (ret) {
  243. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  244. CONFIG_SYS_I2C_EXPANDER_ADDR);
  245. return ret;
  246. }
  247. /* Configure P07-P05 as outputs */
  248. buf[0] = 0x1f;
  249. buf[1] = 0xff;
  250. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
  251. if (ret) {
  252. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  253. CONFIG_SYS_I2C_EXPANDER_ADDR);
  254. }
  255. /* For Ethernet RMII selection
  256. * P07(SelA)=0
  257. * P06(SelB)=1
  258. * P05(SelC)=1
  259. */
  260. if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  261. printf("\nExpander @ 0x%02x read FAILED!!!\n",
  262. CONFIG_SYS_I2C_EXPANDER_ADDR);
  263. }
  264. buf[0] &= 0x1f;
  265. buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
  266. if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  267. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  268. CONFIG_SYS_I2C_EXPANDER_ADDR);
  269. }
  270. /* Set the output as high */
  271. temp = REG(GPIO_BANK2_REG_SET_ADDR);
  272. temp |= (0x01 << 6);
  273. REG(GPIO_BANK2_REG_SET_ADDR) = temp;
  274. /* Set the GPIO direction as output */
  275. temp = REG(GPIO_BANK2_REG_DIR_ADDR);
  276. temp &= ~(0x01 << 6);
  277. REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
  278. return 0;
  279. }
  280. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  281. /*
  282. * Initializes on-board ethernet controllers.
  283. */
  284. int board_eth_init(bd_t *bis)
  285. {
  286. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  287. /* Select RMII fucntion through the expander */
  288. if (rmii_hw_init())
  289. printf("RMII hardware init failed!!!\n");
  290. #endif
  291. if (!davinci_emac_initialize()) {
  292. printf("Error: Ethernet init failed!\n");
  293. return -1;
  294. }
  295. return 0;
  296. }
  297. #endif /* CONFIG_DRIVER_TI_EMAC */