e300.h 4.2 KB

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  1. /*
  2. * Copyright 2004 Freescale Semiconductor, Inc.
  3. * Liberty Eran (liberty@freescale.com)
  4. */
  5. #ifndef __E300_H__
  6. #define __E300_H__
  7. /*
  8. * e300 Processor Version & Revision Numbers
  9. */
  10. #define PVR_83xx 0x80830000
  11. #define PVR_8349_REV10 (PVR_83xx | 0x0010)
  12. #define PVR_8349_REV11 (PVR_83xx | 0x0011)
  13. /*
  14. * Hardware Implementation-Dependent Register 0 (HID0)
  15. */
  16. /* #define HID0 1008 already defined in processor.h */
  17. #define HID0_MASK_MACHINE_CHECK 0x00000000
  18. #define HID0_ENABLE_MACHINE_CHECK 0x80000000
  19. #define HID0_DISABLE_CACHE_PARITY 0x00000000
  20. #define HID0_ENABLE_CACHE_PARITY 0x40000000
  21. #define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
  22. #define HID0_ENABLE_ADDRESS_PARITY 0x20000000
  23. #define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
  24. #define HID0_ENABLE_DATE_PARITY 0x10000000
  25. #define HID0_CORE_CLK_OUT 0x00000000
  26. #define HID0_CORE_CLK_OUT_DIV_2 0x08000000
  27. #define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
  28. #define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
  29. #define HID0_DISABLE_DOSE_MODE 0x00000000
  30. #define HID0_ENABLE_DOSE_MODE 0x00800000
  31. #define HID0_DISABLE_NAP_MODE 0x00000000
  32. #define HID0_ENABLE_NAP_MODE 0x00400000
  33. #define HID0_DISABLE_SLEEP_MODE 0x00000000
  34. #define HID0_ENABLE_SLEEP_MODE 0x00200000
  35. #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
  36. #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
  37. #define HID0_SOFT_RESET 0x00010000
  38. #define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
  39. #define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
  40. #define HID0_DISABLE_DATA_CACHE 0x00000000
  41. #define HID0_ENABLE_DATA_CACHE 0x00004000
  42. #define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
  43. #define HID0_LOCK_DATA_CACHE 0x00001000
  44. #define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
  45. #define HID0_INVALIDATE_DATA_CACHE 0x00000400
  46. #define HID0_DISABLE_M_BIT 0x00000000
  47. #define HID0_ENABLE_M_BIT 0x00000080
  48. #define HID0_FBIOB 0x00000010
  49. #define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
  50. #define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
  51. #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
  52. #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
  53. /*
  54. * Hardware Implementation-Dependent Register 2 (HID2)
  55. */
  56. #define HID2 1011
  57. #define HID2_LET 0x08000000
  58. #define HID2_HBE 0x00040000
  59. #define HID2_IWLCK_000 0x00000000 /* no ways locked */
  60. #define HID2_IWLCK_001 0x00002000 /* way 0 locked */
  61. #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
  62. #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
  63. #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
  64. #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
  65. #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
  66. /* BAT (block address translation */
  67. #define BATU_BEPI_MSK 0xfffe0000
  68. #define BATU_BL_MSK 0x00001ffc
  69. #define BATU_BL_128K 0x00000000
  70. #define BATU_BL_256K 0x00000004
  71. #define BATU_BL_512K 0x0000000c
  72. #define BATU_BL_1M 0x0000001c
  73. #define BATU_BL_2M 0x0000003c
  74. #define BATU_BL_4M 0x0000007c
  75. #define BATU_BL_8M 0x000000fc
  76. #define BATU_BL_16M 0x000001fc
  77. #define BATU_BL_32M 0x000003fc
  78. #define BATU_BL_64M 0x000007fc
  79. #define BATU_BL_128M 0x00000ffc
  80. #define BATU_BL_256M 0x00001ffc
  81. #define BATU_VS 0x00000002
  82. #define BATU_VP 0x00000001
  83. #define BATL_BRPN_MSK 0xfffe0000
  84. #define BATL_WIMG_MSK 0x00000078
  85. #define BATL_WRITETHROUGH 0x00000040
  86. #define BATL_CACHEINHIBIT 0x00000020
  87. #define BATL_MEMCOHERENCE 0x00000010
  88. #define BATL_GUARDEDSTORAGE 0x00000008
  89. #define BATL_PP_MSK 0x00000003
  90. #define BATL_PP_00 0x00000000 /* No access */
  91. #define BATL_PP_01 0x00000001 /* Read-only */
  92. #define BATL_PP_10 0x00000002 /* Read-write */
  93. #define BATL_PP_11 0x00000003
  94. #endif /* __E300_H__ */