usb_ohci.c 44 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
  3. *
  4. * (C) Copyright 2003-2004
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * (C) Copyright 2004
  8. * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
  9. *
  10. * Note: Much of this code has been derived from Linux 2.4
  11. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  12. * (C) Copyright 2000-2002 David Brownell
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - this driver is intended for use with USB Mass Storage Devices
  36. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  37. */
  38. #include <common.h>
  39. #ifdef CONFIG_USB_OHCI
  40. #include <malloc.h>
  41. #include <usb.h>
  42. #include "usb_ohci.h"
  43. #include <mpc5xxx.h>
  44. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  45. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  46. #undef DEBUG
  47. #undef SHOW_INFO
  48. #undef OHCI_FILL_TRACE
  49. /* For initializing controller (mask in an HCFS mode too) */
  50. #define OHCI_CONTROL_INIT \
  51. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  52. #define readl(a) (*((vu_long *)(a)))
  53. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  54. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  55. #ifdef DEBUG
  56. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  57. #else
  58. #define dbg(format, arg...) do {} while(0)
  59. #endif /* DEBUG */
  60. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  61. #ifdef SHOW_INFO
  62. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  63. #else
  64. #define info(format, arg...) do {} while(0)
  65. #endif
  66. #define m16_swap(x) swap_16(x)
  67. #define m32_swap(x) swap_32(x)
  68. #ifdef CONFIG_MPC5200
  69. #define ohci_cpu_to_le16(x) (x)
  70. #define ohci_cpu_to_le32(x) (x)
  71. #else
  72. #define ohci_cpu_to_le16(x) swap_16(x)
  73. #define ohci_cpu_to_le32(x) swap_32(x)
  74. #endif
  75. /* global ohci_t */
  76. static ohci_t gohci;
  77. /* this must be aligned to a 256 byte boundary */
  78. struct ohci_hcca ghcca[1];
  79. /* a pointer to the aligned storage */
  80. struct ohci_hcca *phcca;
  81. /* this allocates EDs for all possible endpoints */
  82. struct ohci_device ohci_dev;
  83. /* urb_priv */
  84. urb_priv_t urb_priv;
  85. /* RHSC flag */
  86. int got_rhsc;
  87. /* device which was disconnected */
  88. struct usb_device *devgone;
  89. /* flag guarding URB transation */
  90. int urb_finished = 0;
  91. /*-------------------------------------------------------------------------*/
  92. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  93. * The erratum (#4) description is incorrect. AMD's workaround waits
  94. * till some bits (mostly reserved) are clear; ok for all revs.
  95. */
  96. #define OHCI_QUIRK_AMD756 0xabcd
  97. #define read_roothub(hc, register, mask) ({ \
  98. u32 temp = readl (&hc->regs->roothub.register); \
  99. if (hc->flags & OHCI_QUIRK_AMD756) \
  100. while (temp & mask) \
  101. temp = readl (&hc->regs->roothub.register); \
  102. temp; })
  103. static u32 roothub_a (struct ohci *hc)
  104. { return read_roothub (hc, a, 0xfc0fe000); }
  105. static inline u32 roothub_b (struct ohci *hc)
  106. { return readl (&hc->regs->roothub.b); }
  107. static inline u32 roothub_status (struct ohci *hc)
  108. { return readl (&hc->regs->roothub.status); }
  109. static u32 roothub_portstatus (struct ohci *hc, int i)
  110. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  111. /* forward declaration */
  112. static int hc_interrupt (void);
  113. static void
  114. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  115. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  116. /*-------------------------------------------------------------------------*
  117. * URB support functions
  118. *-------------------------------------------------------------------------*/
  119. /* free HCD-private data associated with this URB */
  120. static void urb_free_priv (urb_priv_t * urb)
  121. {
  122. int i;
  123. int last;
  124. struct td * td;
  125. last = urb->length - 1;
  126. if (last >= 0) {
  127. for (i = 0; i <= last; i++) {
  128. td = urb->td[i];
  129. if (td) {
  130. td->usb_dev = NULL;
  131. urb->td[i] = NULL;
  132. }
  133. }
  134. }
  135. }
  136. /*-------------------------------------------------------------------------*/
  137. #ifdef DEBUG
  138. static int sohci_get_current_frame_number (struct usb_device * dev);
  139. /* debug| print the main components of an URB
  140. * small: 0) header + data packets 1) just header */
  141. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  142. int transfer_len, struct devrequest * setup, char * str, int small)
  143. {
  144. urb_priv_t * purb = &urb_priv;
  145. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  146. str,
  147. sohci_get_current_frame_number (dev),
  148. usb_pipedevice (pipe),
  149. usb_pipeendpoint (pipe),
  150. usb_pipeout (pipe)? 'O': 'I',
  151. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  152. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  153. purb->actual_length,
  154. transfer_len, dev->status);
  155. #ifdef OHCI_VERBOSE_DEBUG
  156. if (!small) {
  157. int i, len;
  158. if (usb_pipecontrol (pipe)) {
  159. printf (__FILE__ ": cmd(8):");
  160. for (i = 0; i < 8 ; i++)
  161. printf (" %02x", ((__u8 *) setup) [i]);
  162. printf ("\n");
  163. }
  164. if (transfer_len > 0 && buffer) {
  165. printf (__FILE__ ": data(%d/%d):",
  166. purb->actual_length,
  167. transfer_len);
  168. len = usb_pipeout (pipe)?
  169. transfer_len: purb->actual_length;
  170. for (i = 0; i < 16 && i < len; i++)
  171. printf (" %02x", ((__u8 *) buffer) [i]);
  172. printf ("%s\n", i < len? "...": "");
  173. }
  174. }
  175. #endif
  176. }
  177. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  178. void ep_print_int_eds (ohci_t *ohci, char * str) {
  179. int i, j;
  180. __u32 * ed_p;
  181. for (i= 0; i < 32; i++) {
  182. j = 5;
  183. ed_p = &(ohci->hcca->int_table [i]);
  184. if (*ed_p == 0)
  185. continue;
  186. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  187. while (*ed_p != 0 && j--) {
  188. ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
  189. printf (" ed: %4x;", ed->hwINFO);
  190. ed_p = &ed->hwNextED;
  191. }
  192. printf ("\n");
  193. }
  194. }
  195. static void ohci_dump_intr_mask (char *label, __u32 mask)
  196. {
  197. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  198. label,
  199. mask,
  200. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  201. (mask & OHCI_INTR_OC) ? " OC" : "",
  202. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  203. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  204. (mask & OHCI_INTR_UE) ? " UE" : "",
  205. (mask & OHCI_INTR_RD) ? " RD" : "",
  206. (mask & OHCI_INTR_SF) ? " SF" : "",
  207. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  208. (mask & OHCI_INTR_SO) ? " SO" : ""
  209. );
  210. }
  211. static void maybe_print_eds (char *label, __u32 value)
  212. {
  213. ed_t *edp = (ed_t *)value;
  214. if (value) {
  215. dbg ("%s %08x", label, value);
  216. dbg ("%08x", edp->hwINFO);
  217. dbg ("%08x", edp->hwTailP);
  218. dbg ("%08x", edp->hwHeadP);
  219. dbg ("%08x", edp->hwNextED);
  220. }
  221. }
  222. static char * hcfs2string (int state)
  223. {
  224. switch (state) {
  225. case OHCI_USB_RESET: return "reset";
  226. case OHCI_USB_RESUME: return "resume";
  227. case OHCI_USB_OPER: return "operational";
  228. case OHCI_USB_SUSPEND: return "suspend";
  229. }
  230. return "?";
  231. }
  232. /* dump control and status registers */
  233. static void ohci_dump_status (ohci_t *controller)
  234. {
  235. struct ohci_regs *regs = controller->regs;
  236. __u32 temp;
  237. temp = readl (&regs->revision) & 0xff;
  238. if (temp != 0x10)
  239. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  240. temp = readl (&regs->control);
  241. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  242. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  243. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  244. (temp & OHCI_CTRL_IR) ? " IR" : "",
  245. hcfs2string (temp & OHCI_CTRL_HCFS),
  246. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  247. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  248. (temp & OHCI_CTRL_IE) ? " IE" : "",
  249. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  250. temp & OHCI_CTRL_CBSR
  251. );
  252. temp = readl (&regs->cmdstatus);
  253. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  254. (temp & OHCI_SOC) >> 16,
  255. (temp & OHCI_OCR) ? " OCR" : "",
  256. (temp & OHCI_BLF) ? " BLF" : "",
  257. (temp & OHCI_CLF) ? " CLF" : "",
  258. (temp & OHCI_HCR) ? " HCR" : ""
  259. );
  260. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  261. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  262. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  263. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  264. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  265. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  266. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  267. maybe_print_eds ("donehead", readl (&regs->donehead));
  268. }
  269. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  270. {
  271. __u32 temp, ndp, i;
  272. temp = roothub_a (controller);
  273. ndp = (temp & RH_A_NDP);
  274. if (verbose) {
  275. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  276. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  277. (temp & RH_A_NOCP) ? " NOCP" : "",
  278. (temp & RH_A_OCPM) ? " OCPM" : "",
  279. (temp & RH_A_DT) ? " DT" : "",
  280. (temp & RH_A_NPS) ? " NPS" : "",
  281. (temp & RH_A_PSM) ? " PSM" : "",
  282. ndp
  283. );
  284. temp = roothub_b (controller);
  285. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  286. temp,
  287. (temp & RH_B_PPCM) >> 16,
  288. (temp & RH_B_DR)
  289. );
  290. temp = roothub_status (controller);
  291. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  292. temp,
  293. (temp & RH_HS_CRWE) ? " CRWE" : "",
  294. (temp & RH_HS_OCIC) ? " OCIC" : "",
  295. (temp & RH_HS_LPSC) ? " LPSC" : "",
  296. (temp & RH_HS_DRWE) ? " DRWE" : "",
  297. (temp & RH_HS_OCI) ? " OCI" : "",
  298. (temp & RH_HS_LPS) ? " LPS" : ""
  299. );
  300. }
  301. for (i = 0; i < ndp; i++) {
  302. temp = roothub_portstatus (controller, i);
  303. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  304. i,
  305. temp,
  306. (temp & RH_PS_PRSC) ? " PRSC" : "",
  307. (temp & RH_PS_OCIC) ? " OCIC" : "",
  308. (temp & RH_PS_PSSC) ? " PSSC" : "",
  309. (temp & RH_PS_PESC) ? " PESC" : "",
  310. (temp & RH_PS_CSC) ? " CSC" : "",
  311. (temp & RH_PS_LSDA) ? " LSDA" : "",
  312. (temp & RH_PS_PPS) ? " PPS" : "",
  313. (temp & RH_PS_PRS) ? " PRS" : "",
  314. (temp & RH_PS_POCI) ? " POCI" : "",
  315. (temp & RH_PS_PSS) ? " PSS" : "",
  316. (temp & RH_PS_PES) ? " PES" : "",
  317. (temp & RH_PS_CCS) ? " CCS" : ""
  318. );
  319. }
  320. }
  321. static void ohci_dump (ohci_t *controller, int verbose)
  322. {
  323. dbg ("OHCI controller usb-%s state", controller->slot_name);
  324. /* dumps some of the state we know about */
  325. ohci_dump_status (controller);
  326. if (verbose)
  327. ep_print_int_eds (controller, "hcca");
  328. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  329. ohci_dump_roothub (controller, 1);
  330. }
  331. #endif /* DEBUG */
  332. /*-------------------------------------------------------------------------*
  333. * Interface functions (URB)
  334. *-------------------------------------------------------------------------*/
  335. /* get a transfer request */
  336. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  337. int transfer_len, struct devrequest *setup, int interval)
  338. {
  339. ohci_t *ohci;
  340. ed_t * ed;
  341. urb_priv_t *purb_priv;
  342. int i, size = 0;
  343. ohci = &gohci;
  344. /* when controller's hung, permit only roothub cleanup attempts
  345. * such as powering down ports */
  346. if (ohci->disabled) {
  347. err("sohci_submit_job: EPIPE");
  348. return -1;
  349. }
  350. /* if we have an unfinished URB from previous transaction let's
  351. * fail and scream as quickly as possible so as not to corrupt
  352. * further communication */
  353. if (!urb_finished) {
  354. err("sohci_submit_job: URB NOT FINISHED");
  355. return -1;
  356. }
  357. /* we're about to begin a new transaction here so mark the URB unfinished */
  358. urb_finished = 0;
  359. /* every endpoint has a ed, locate and fill it */
  360. if (!(ed = ep_add_ed (dev, pipe))) {
  361. err("sohci_submit_job: ENOMEM");
  362. return -1;
  363. }
  364. /* for the private part of the URB we need the number of TDs (size) */
  365. switch (usb_pipetype (pipe)) {
  366. case PIPE_BULK: /* one TD for every 4096 Byte */
  367. size = (transfer_len - 1) / 4096 + 1;
  368. break;
  369. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  370. size = (transfer_len == 0)? 2:
  371. (transfer_len - 1) / 4096 + 3;
  372. break;
  373. }
  374. if (size >= (N_URB_TD - 1)) {
  375. err("need %d TDs, only have %d", size, N_URB_TD);
  376. return -1;
  377. }
  378. purb_priv = &urb_priv;
  379. purb_priv->pipe = pipe;
  380. /* fill the private part of the URB */
  381. purb_priv->length = size;
  382. purb_priv->ed = ed;
  383. purb_priv->actual_length = 0;
  384. /* allocate the TDs */
  385. /* note that td[0] was allocated in ep_add_ed */
  386. for (i = 0; i < size; i++) {
  387. purb_priv->td[i] = td_alloc (dev);
  388. if (!purb_priv->td[i]) {
  389. purb_priv->length = i;
  390. urb_free_priv (purb_priv);
  391. err("sohci_submit_job: ENOMEM");
  392. return -1;
  393. }
  394. }
  395. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  396. urb_free_priv (purb_priv);
  397. err("sohci_submit_job: EINVAL");
  398. return -1;
  399. }
  400. /* link the ed into a chain if is not already */
  401. if (ed->state != ED_OPER)
  402. ep_link (ohci, ed);
  403. /* fill the TDs and link it to the ed */
  404. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  405. return 0;
  406. }
  407. /*-------------------------------------------------------------------------*/
  408. #ifdef DEBUG
  409. /* tell us the current USB frame number */
  410. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  411. {
  412. ohci_t *ohci = &gohci;
  413. return ohci_cpu_to_le16 (ohci->hcca->frame_no);
  414. }
  415. #endif
  416. /*-------------------------------------------------------------------------*
  417. * ED handling functions
  418. *-------------------------------------------------------------------------*/
  419. /* link an ed into one of the HC chains */
  420. static int ep_link (ohci_t *ohci, ed_t *edi)
  421. {
  422. volatile ed_t *ed = edi;
  423. ed->state = ED_OPER;
  424. switch (ed->type) {
  425. case PIPE_CONTROL:
  426. ed->hwNextED = 0;
  427. if (ohci->ed_controltail == NULL) {
  428. writel (ed, &ohci->regs->ed_controlhead);
  429. } else {
  430. ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  431. }
  432. ed->ed_prev = ohci->ed_controltail;
  433. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  434. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  435. ohci->hc_control |= OHCI_CTRL_CLE;
  436. writel (ohci->hc_control, &ohci->regs->control);
  437. }
  438. ohci->ed_controltail = edi;
  439. break;
  440. case PIPE_BULK:
  441. ed->hwNextED = 0;
  442. if (ohci->ed_bulktail == NULL) {
  443. writel (ed, &ohci->regs->ed_bulkhead);
  444. } else {
  445. ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  446. }
  447. ed->ed_prev = ohci->ed_bulktail;
  448. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  449. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  450. ohci->hc_control |= OHCI_CTRL_BLE;
  451. writel (ohci->hc_control, &ohci->regs->control);
  452. }
  453. ohci->ed_bulktail = edi;
  454. break;
  455. }
  456. return 0;
  457. }
  458. /*-------------------------------------------------------------------------*/
  459. /* unlink an ed from one of the HC chains.
  460. * just the link to the ed is unlinked.
  461. * the link from the ed still points to another operational ed or 0
  462. * so the HC can eventually finish the processing of the unlinked ed */
  463. static int ep_unlink (ohci_t *ohci, ed_t *edi)
  464. {
  465. volatile ed_t *ed = edi;
  466. ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
  467. switch (ed->type) {
  468. case PIPE_CONTROL:
  469. if (ed->ed_prev == NULL) {
  470. if (!ed->hwNextED) {
  471. ohci->hc_control &= ~OHCI_CTRL_CLE;
  472. writel (ohci->hc_control, &ohci->regs->control);
  473. }
  474. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  475. } else {
  476. ed->ed_prev->hwNextED = ed->hwNextED;
  477. }
  478. if (ohci->ed_controltail == ed) {
  479. ohci->ed_controltail = ed->ed_prev;
  480. } else {
  481. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  482. }
  483. break;
  484. case PIPE_BULK:
  485. if (ed->ed_prev == NULL) {
  486. if (!ed->hwNextED) {
  487. ohci->hc_control &= ~OHCI_CTRL_BLE;
  488. writel (ohci->hc_control, &ohci->regs->control);
  489. }
  490. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  491. } else {
  492. ed->ed_prev->hwNextED = ed->hwNextED;
  493. }
  494. if (ohci->ed_bulktail == ed) {
  495. ohci->ed_bulktail = ed->ed_prev;
  496. } else {
  497. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  498. }
  499. break;
  500. }
  501. ed->state = ED_UNLINK;
  502. return 0;
  503. }
  504. /*-------------------------------------------------------------------------*/
  505. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  506. * but the USB stack is a little bit stateless so we do it at every transaction
  507. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  508. * in all other cases the state is left unchanged
  509. * the ed info fields are setted anyway even though most of them should not change */
  510. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  511. {
  512. td_t *td;
  513. ed_t *ed_ret;
  514. volatile ed_t *ed;
  515. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  516. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  517. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  518. err("ep_add_ed: pending delete");
  519. /* pending delete request */
  520. return NULL;
  521. }
  522. if (ed->state == ED_NEW) {
  523. ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
  524. /* dummy td; end of td list for ed */
  525. td = td_alloc (usb_dev);
  526. ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
  527. ed->hwHeadP = ed->hwTailP;
  528. ed->state = ED_UNLINK;
  529. ed->type = usb_pipetype (pipe);
  530. ohci_dev.ed_cnt++;
  531. }
  532. ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
  533. | usb_pipeendpoint (pipe) << 7
  534. | (usb_pipeisoc (pipe)? 0x8000: 0)
  535. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  536. | usb_pipeslow (pipe) << 13
  537. | usb_maxpacket (usb_dev, pipe) << 16);
  538. return ed_ret;
  539. }
  540. /*-------------------------------------------------------------------------*
  541. * TD handling functions
  542. *-------------------------------------------------------------------------*/
  543. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  544. static void td_fill (ohci_t *ohci, unsigned int info,
  545. void *data, int len,
  546. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  547. {
  548. volatile td_t *td, *td_pt;
  549. #ifdef OHCI_FILL_TRACE
  550. int i;
  551. #endif
  552. if (index > urb_priv->length) {
  553. err("index > length");
  554. return;
  555. }
  556. /* use this td as the next dummy */
  557. td_pt = urb_priv->td [index];
  558. td_pt->hwNextTD = 0;
  559. /* fill the old dummy TD */
  560. td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
  561. td->ed = urb_priv->ed;
  562. td->next_dl_td = NULL;
  563. td->index = index;
  564. td->data = (__u32)data;
  565. #ifdef OHCI_FILL_TRACE
  566. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  567. for (i = 0; i < len; i++)
  568. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  569. printf("\n");
  570. }
  571. #endif
  572. if (!len)
  573. data = 0;
  574. td->hwINFO = ohci_cpu_to_le32 (info);
  575. td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
  576. if (data)
  577. td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
  578. else
  579. td->hwBE = 0;
  580. td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
  581. /* append to queue */
  582. td->ed->hwTailP = td->hwNextTD;
  583. }
  584. /*-------------------------------------------------------------------------*/
  585. /* prepare all TDs of a transfer */
  586. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  587. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  588. {
  589. ohci_t *ohci = &gohci;
  590. int data_len = transfer_len;
  591. void *data;
  592. int cnt = 0;
  593. __u32 info = 0;
  594. unsigned int toggle = 0;
  595. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  596. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  597. toggle = TD_T_TOGGLE;
  598. } else {
  599. toggle = TD_T_DATA0;
  600. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  601. }
  602. urb->td_cnt = 0;
  603. if (data_len)
  604. data = buffer;
  605. else
  606. data = 0;
  607. switch (usb_pipetype (pipe)) {
  608. case PIPE_BULK:
  609. info = usb_pipeout (pipe)?
  610. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  611. while(data_len > 4096) {
  612. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  613. data += 4096; data_len -= 4096; cnt++;
  614. }
  615. info = usb_pipeout (pipe)?
  616. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  617. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  618. cnt++;
  619. if (!ohci->sleeping)
  620. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  621. break;
  622. case PIPE_CONTROL:
  623. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  624. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  625. if (data_len > 0) {
  626. info = usb_pipeout (pipe)?
  627. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  628. /* NOTE: mishandles transfers >8K, some >4K */
  629. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  630. }
  631. info = usb_pipeout (pipe)?
  632. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  633. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  634. if (!ohci->sleeping)
  635. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  636. break;
  637. }
  638. if (urb->length != cnt)
  639. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  640. }
  641. /*-------------------------------------------------------------------------*
  642. * Done List handling functions
  643. *-------------------------------------------------------------------------*/
  644. /* calculate the transfer length and update the urb */
  645. static void dl_transfer_length(td_t * td)
  646. {
  647. __u32 tdINFO, tdBE, tdCBP;
  648. urb_priv_t *lurb_priv = &urb_priv;
  649. tdINFO = ohci_cpu_to_le32 (td->hwINFO);
  650. tdBE = ohci_cpu_to_le32 (td->hwBE);
  651. tdCBP = ohci_cpu_to_le32 (td->hwCBP);
  652. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  653. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  654. if (tdBE != 0) {
  655. if (td->hwCBP == 0)
  656. lurb_priv->actual_length += tdBE - td->data + 1;
  657. else
  658. lurb_priv->actual_length += tdCBP - td->data;
  659. }
  660. }
  661. }
  662. /*-------------------------------------------------------------------------*/
  663. /* replies to the request have to be on a FIFO basis so
  664. * we reverse the reversed done-list */
  665. static td_t * dl_reverse_done_list (ohci_t *ohci)
  666. {
  667. __u32 td_list_hc;
  668. td_t *td_rev = NULL;
  669. td_t *td_list = NULL;
  670. urb_priv_t *lurb_priv = NULL;
  671. td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
  672. ohci->hcca->done_head = 0;
  673. while (td_list_hc) {
  674. td_list = (td_t *)td_list_hc;
  675. if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
  676. lurb_priv = &urb_priv;
  677. dbg(" USB-error/status: %x : %p",
  678. TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
  679. if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
  680. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  681. td_list->ed->hwHeadP =
  682. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
  683. (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
  684. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  685. } else
  686. td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
  687. }
  688. #ifdef CONFIG_MPC5200
  689. td_list->hwNextTD = 0;
  690. #endif
  691. }
  692. td_list->next_dl_td = td_rev;
  693. td_rev = td_list;
  694. td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
  695. }
  696. return td_list;
  697. }
  698. /*-------------------------------------------------------------------------*/
  699. /* td done list */
  700. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  701. {
  702. td_t *td_list_next = NULL;
  703. ed_t *ed;
  704. int cc = 0;
  705. int stat = 0;
  706. /* urb_t *urb; */
  707. urb_priv_t *lurb_priv;
  708. __u32 tdINFO, edHeadP, edTailP;
  709. while (td_list) {
  710. td_list_next = td_list->next_dl_td;
  711. lurb_priv = &urb_priv;
  712. tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
  713. ed = td_list->ed;
  714. dl_transfer_length(td_list);
  715. /* error code of transfer */
  716. cc = TD_CC_GET (tdINFO);
  717. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  718. if ((ed->state & (ED_OPER | ED_UNLINK))
  719. && (lurb_priv->state != URB_DEL)) {
  720. dbg("ConditionCode %#x", cc);
  721. stat = cc_to_error[cc];
  722. urb_finished = 1;
  723. }
  724. }
  725. if (ed->state != ED_NEW) {
  726. edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
  727. edTailP = ohci_cpu_to_le32 (ed->hwTailP);
  728. /* unlink eds if they are not busy */
  729. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  730. ep_unlink (ohci, ed);
  731. }
  732. td_list = td_list_next;
  733. }
  734. return stat;
  735. }
  736. /*-------------------------------------------------------------------------*
  737. * Virtual Root Hub
  738. *-------------------------------------------------------------------------*/
  739. /* Device descriptor */
  740. static __u8 root_hub_dev_des[] =
  741. {
  742. 0x12, /* __u8 bLength; */
  743. 0x01, /* __u8 bDescriptorType; Device */
  744. 0x10, /* __u16 bcdUSB; v1.1 */
  745. 0x01,
  746. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  747. 0x00, /* __u8 bDeviceSubClass; */
  748. 0x00, /* __u8 bDeviceProtocol; */
  749. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  750. 0x00, /* __u16 idVendor; */
  751. 0x00,
  752. 0x00, /* __u16 idProduct; */
  753. 0x00,
  754. 0x00, /* __u16 bcdDevice; */
  755. 0x00,
  756. 0x00, /* __u8 iManufacturer; */
  757. 0x01, /* __u8 iProduct; */
  758. 0x00, /* __u8 iSerialNumber; */
  759. 0x01 /* __u8 bNumConfigurations; */
  760. };
  761. /* Configuration descriptor */
  762. static __u8 root_hub_config_des[] =
  763. {
  764. 0x09, /* __u8 bLength; */
  765. 0x02, /* __u8 bDescriptorType; Configuration */
  766. 0x19, /* __u16 wTotalLength; */
  767. 0x00,
  768. 0x01, /* __u8 bNumInterfaces; */
  769. 0x01, /* __u8 bConfigurationValue; */
  770. 0x00, /* __u8 iConfiguration; */
  771. 0x40, /* __u8 bmAttributes;
  772. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  773. 0x00, /* __u8 MaxPower; */
  774. /* interface */
  775. 0x09, /* __u8 if_bLength; */
  776. 0x04, /* __u8 if_bDescriptorType; Interface */
  777. 0x00, /* __u8 if_bInterfaceNumber; */
  778. 0x00, /* __u8 if_bAlternateSetting; */
  779. 0x01, /* __u8 if_bNumEndpoints; */
  780. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  781. 0x00, /* __u8 if_bInterfaceSubClass; */
  782. 0x00, /* __u8 if_bInterfaceProtocol; */
  783. 0x00, /* __u8 if_iInterface; */
  784. /* endpoint */
  785. 0x07, /* __u8 ep_bLength; */
  786. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  787. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  788. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  789. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  790. 0x00,
  791. 0xff /* __u8 ep_bInterval; 255 ms */
  792. };
  793. static unsigned char root_hub_str_index0[] =
  794. {
  795. 0x04, /* __u8 bLength; */
  796. 0x03, /* __u8 bDescriptorType; String-descriptor */
  797. 0x09, /* __u8 lang ID */
  798. 0x04, /* __u8 lang ID */
  799. };
  800. static unsigned char root_hub_str_index1[] =
  801. {
  802. 28, /* __u8 bLength; */
  803. 0x03, /* __u8 bDescriptorType; String-descriptor */
  804. 'O', /* __u8 Unicode */
  805. 0, /* __u8 Unicode */
  806. 'H', /* __u8 Unicode */
  807. 0, /* __u8 Unicode */
  808. 'C', /* __u8 Unicode */
  809. 0, /* __u8 Unicode */
  810. 'I', /* __u8 Unicode */
  811. 0, /* __u8 Unicode */
  812. ' ', /* __u8 Unicode */
  813. 0, /* __u8 Unicode */
  814. 'R', /* __u8 Unicode */
  815. 0, /* __u8 Unicode */
  816. 'o', /* __u8 Unicode */
  817. 0, /* __u8 Unicode */
  818. 'o', /* __u8 Unicode */
  819. 0, /* __u8 Unicode */
  820. 't', /* __u8 Unicode */
  821. 0, /* __u8 Unicode */
  822. ' ', /* __u8 Unicode */
  823. 0, /* __u8 Unicode */
  824. 'H', /* __u8 Unicode */
  825. 0, /* __u8 Unicode */
  826. 'u', /* __u8 Unicode */
  827. 0, /* __u8 Unicode */
  828. 'b', /* __u8 Unicode */
  829. 0, /* __u8 Unicode */
  830. };
  831. /* Hub class-specific descriptor is constructed dynamically */
  832. /*-------------------------------------------------------------------------*/
  833. #define OK(x) len = (x); break
  834. #ifdef DEBUG
  835. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  836. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  837. #else
  838. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  839. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  840. #endif
  841. #define RD_RH_STAT roothub_status(&gohci)
  842. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  843. /* request to virtual root hub */
  844. int rh_check_port_status(ohci_t *controller)
  845. {
  846. __u32 temp, ndp, i;
  847. int res;
  848. res = -1;
  849. temp = roothub_a (controller);
  850. ndp = (temp & RH_A_NDP);
  851. for (i = 0; i < ndp; i++) {
  852. temp = roothub_portstatus (controller, i);
  853. /* check for a device disconnect */
  854. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  855. (RH_PS_PESC | RH_PS_CSC)) &&
  856. ((temp & RH_PS_CCS) == 0)) {
  857. res = i;
  858. break;
  859. }
  860. }
  861. return res;
  862. }
  863. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  864. void *buffer, int transfer_len, struct devrequest *cmd)
  865. {
  866. void * data = buffer;
  867. int leni = transfer_len;
  868. int len = 0;
  869. int stat = 0;
  870. __u32 datab[4];
  871. __u8 *data_buf = (__u8 *)datab;
  872. __u16 bmRType_bReq;
  873. __u16 wValue;
  874. __u16 wIndex;
  875. __u16 wLength;
  876. #ifdef DEBUG
  877. urb_priv.actual_length = 0;
  878. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  879. #endif
  880. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  881. info("Root-Hub submit IRQ: NOT implemented");
  882. return 0;
  883. }
  884. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  885. wValue = m16_swap (cmd->value);
  886. wIndex = m16_swap (cmd->index);
  887. wLength = m16_swap (cmd->length);
  888. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  889. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  890. switch (bmRType_bReq) {
  891. /* Request Destination:
  892. without flags: Device,
  893. RH_INTERFACE: interface,
  894. RH_ENDPOINT: endpoint,
  895. RH_CLASS means HUB here,
  896. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  897. */
  898. case RH_GET_STATUS:
  899. *(__u16 *) data_buf = m16_swap (1); OK (2);
  900. case RH_GET_STATUS | RH_INTERFACE:
  901. *(__u16 *) data_buf = m16_swap (0); OK (2);
  902. case RH_GET_STATUS | RH_ENDPOINT:
  903. *(__u16 *) data_buf = m16_swap (0); OK (2);
  904. case RH_GET_STATUS | RH_CLASS:
  905. *(__u32 *) data_buf = m32_swap (
  906. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  907. OK (4);
  908. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  909. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  910. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  911. switch (wValue) {
  912. case (RH_ENDPOINT_STALL): OK (0);
  913. }
  914. break;
  915. case RH_CLEAR_FEATURE | RH_CLASS:
  916. switch (wValue) {
  917. case RH_C_HUB_LOCAL_POWER:
  918. OK(0);
  919. case (RH_C_HUB_OVER_CURRENT):
  920. WR_RH_STAT(RH_HS_OCIC); OK (0);
  921. }
  922. break;
  923. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  924. switch (wValue) {
  925. case (RH_PORT_ENABLE):
  926. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  927. case (RH_PORT_SUSPEND):
  928. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  929. case (RH_PORT_POWER):
  930. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  931. case (RH_C_PORT_CONNECTION):
  932. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  933. case (RH_C_PORT_ENABLE):
  934. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  935. case (RH_C_PORT_SUSPEND):
  936. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  937. case (RH_C_PORT_OVER_CURRENT):
  938. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  939. case (RH_C_PORT_RESET):
  940. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  941. }
  942. break;
  943. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  944. switch (wValue) {
  945. case (RH_PORT_SUSPEND):
  946. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  947. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  948. if (RD_RH_PORTSTAT & RH_PS_CCS)
  949. WR_RH_PORTSTAT (RH_PS_PRS);
  950. OK (0);
  951. case (RH_PORT_POWER):
  952. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  953. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  954. if (RD_RH_PORTSTAT & RH_PS_CCS)
  955. WR_RH_PORTSTAT (RH_PS_PES );
  956. OK (0);
  957. }
  958. break;
  959. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  960. case RH_GET_DESCRIPTOR:
  961. switch ((wValue & 0xff00) >> 8) {
  962. case (0x01): /* device descriptor */
  963. len = min_t(unsigned int,
  964. leni,
  965. min_t(unsigned int,
  966. sizeof (root_hub_dev_des),
  967. wLength));
  968. data_buf = root_hub_dev_des; OK(len);
  969. case (0x02): /* configuration descriptor */
  970. len = min_t(unsigned int,
  971. leni,
  972. min_t(unsigned int,
  973. sizeof (root_hub_config_des),
  974. wLength));
  975. data_buf = root_hub_config_des; OK(len);
  976. case (0x03): /* string descriptors */
  977. if(wValue==0x0300) {
  978. len = min_t(unsigned int,
  979. leni,
  980. min_t(unsigned int,
  981. sizeof (root_hub_str_index0),
  982. wLength));
  983. data_buf = root_hub_str_index0;
  984. OK(len);
  985. }
  986. if(wValue==0x0301) {
  987. len = min_t(unsigned int,
  988. leni,
  989. min_t(unsigned int,
  990. sizeof (root_hub_str_index1),
  991. wLength));
  992. data_buf = root_hub_str_index1;
  993. OK(len);
  994. }
  995. default:
  996. stat = USB_ST_STALLED;
  997. }
  998. break;
  999. case RH_GET_DESCRIPTOR | RH_CLASS:
  1000. {
  1001. __u32 temp = roothub_a (&gohci);
  1002. data_buf [0] = 9; /* min length; */
  1003. data_buf [1] = 0x29;
  1004. data_buf [2] = temp & RH_A_NDP;
  1005. data_buf [3] = 0;
  1006. if (temp & RH_A_PSM) /* per-port power switching? */
  1007. data_buf [3] |= 0x1;
  1008. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1009. data_buf [3] |= 0x10;
  1010. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1011. data_buf [3] |= 0x8;
  1012. /* corresponds to data_buf[4-7] */
  1013. datab [1] = 0;
  1014. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1015. temp = roothub_b (&gohci);
  1016. data_buf [7] = temp & RH_B_DR;
  1017. if (data_buf [2] < 7) {
  1018. data_buf [8] = 0xff;
  1019. } else {
  1020. data_buf [0] += 2;
  1021. data_buf [8] = (temp & RH_B_DR) >> 8;
  1022. data_buf [10] = data_buf [9] = 0xff;
  1023. }
  1024. len = min_t(unsigned int, leni,
  1025. min_t(unsigned int, data_buf [0], wLength));
  1026. OK (len);
  1027. }
  1028. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1029. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1030. default:
  1031. dbg ("unsupported root hub command");
  1032. stat = USB_ST_STALLED;
  1033. }
  1034. #ifdef DEBUG
  1035. ohci_dump_roothub (&gohci, 1);
  1036. #endif
  1037. len = min_t(int, len, leni);
  1038. if (data != data_buf)
  1039. memcpy (data, data_buf, len);
  1040. dev->act_len = len;
  1041. dev->status = stat;
  1042. #ifdef DEBUG
  1043. if (transfer_len)
  1044. urb_priv.actual_length = transfer_len;
  1045. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1046. #endif
  1047. return stat;
  1048. }
  1049. /*-------------------------------------------------------------------------*/
  1050. /* common code for handling submit messages - used for all but root hub */
  1051. /* accesses. */
  1052. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1053. int transfer_len, struct devrequest *setup, int interval)
  1054. {
  1055. int stat = 0;
  1056. int maxsize = usb_maxpacket(dev, pipe);
  1057. int timeout;
  1058. /* device pulled? Shortcut the action. */
  1059. if (devgone == dev) {
  1060. dev->status = USB_ST_CRC_ERR;
  1061. return 0;
  1062. }
  1063. #ifdef DEBUG
  1064. urb_priv.actual_length = 0;
  1065. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1066. #endif
  1067. if (!maxsize) {
  1068. err("submit_common_message: pipesize for pipe %lx is zero",
  1069. pipe);
  1070. return -1;
  1071. }
  1072. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1073. err("sohci_submit_job failed");
  1074. return -1;
  1075. }
  1076. /* allow more time for a BULK device to react - some are slow */
  1077. #define BULK_TO 5000 /* timeout in milliseconds */
  1078. if (usb_pipetype (pipe) == PIPE_BULK)
  1079. timeout = BULK_TO;
  1080. else
  1081. timeout = 100;
  1082. /* wait for it to complete */
  1083. for (;;) {
  1084. /* check whether the controller is done */
  1085. stat = hc_interrupt();
  1086. if (stat < 0) {
  1087. stat = USB_ST_CRC_ERR;
  1088. break;
  1089. }
  1090. /* NOTE: since we are not interrupt driven in U-Boot and always
  1091. * handle only one URB at a time, we cannot assume the
  1092. * transaction finished on the first successful return from
  1093. * hc_interrupt().. unless the flag for current URB is set,
  1094. * meaning that all TD's to/from device got actually
  1095. * transferred and processed. If the current URB is not
  1096. * finished we need to re-iterate this loop so as
  1097. * hc_interrupt() gets called again as there needs to be some
  1098. * more TD's to process still */
  1099. if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
  1100. /* 0xff is returned for an SF-interrupt */
  1101. break;
  1102. }
  1103. if (--timeout) {
  1104. wait_ms(1);
  1105. if (!urb_finished)
  1106. dbg("\%");
  1107. } else {
  1108. err("CTL:TIMEOUT ");
  1109. dbg("submit_common_msg: TO status %x\n", stat);
  1110. stat = USB_ST_CRC_ERR;
  1111. urb_finished = 1;
  1112. break;
  1113. }
  1114. }
  1115. #if 0
  1116. /* we got an Root Hub Status Change interrupt */
  1117. if (got_rhsc) {
  1118. #ifdef DEBUG
  1119. ohci_dump_roothub (&gohci, 1);
  1120. #endif
  1121. got_rhsc = 0;
  1122. /* abuse timeout */
  1123. timeout = rh_check_port_status(&gohci);
  1124. if (timeout >= 0) {
  1125. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1126. /* the called routine adds 1 to the passed value */
  1127. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1128. #endif
  1129. /*
  1130. * XXX
  1131. * This is potentially dangerous because it assumes
  1132. * that only one device is ever plugged in!
  1133. */
  1134. devgone = dev;
  1135. }
  1136. }
  1137. #endif
  1138. dev->status = stat;
  1139. dev->act_len = transfer_len;
  1140. #ifdef DEBUG
  1141. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1142. #endif
  1143. /* free TDs in urb_priv */
  1144. urb_free_priv (&urb_priv);
  1145. return 0;
  1146. }
  1147. /* submit routines called from usb.c */
  1148. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1149. int transfer_len)
  1150. {
  1151. info("submit_bulk_msg");
  1152. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1153. }
  1154. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1155. int transfer_len, struct devrequest *setup)
  1156. {
  1157. int maxsize = usb_maxpacket(dev, pipe);
  1158. info("submit_control_msg");
  1159. #ifdef DEBUG
  1160. urb_priv.actual_length = 0;
  1161. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1162. #endif
  1163. if (!maxsize) {
  1164. err("submit_control_message: pipesize for pipe %lx is zero",
  1165. pipe);
  1166. return -1;
  1167. }
  1168. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1169. gohci.rh.dev = dev;
  1170. /* root hub - redirect */
  1171. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1172. setup);
  1173. }
  1174. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1175. }
  1176. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1177. int transfer_len, int interval)
  1178. {
  1179. info("submit_int_msg");
  1180. return -1;
  1181. }
  1182. /*-------------------------------------------------------------------------*
  1183. * HC functions
  1184. *-------------------------------------------------------------------------*/
  1185. /* reset the HC and BUS */
  1186. static int hc_reset (ohci_t *ohci)
  1187. {
  1188. int timeout = 30;
  1189. int smm_timeout = 50; /* 0,5 sec */
  1190. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1191. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1192. info("USB HC TakeOver from SMM");
  1193. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1194. wait_ms (10);
  1195. if (--smm_timeout == 0) {
  1196. err("USB HC TakeOver failed!");
  1197. return -1;
  1198. }
  1199. }
  1200. }
  1201. /* Disable HC interrupts */
  1202. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1203. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1204. ohci->slot_name,
  1205. readl (&ohci->regs->control));
  1206. /* Reset USB (needed by some controllers) */
  1207. ohci->hc_control = 0;
  1208. writel (ohci->hc_control, &ohci->regs->control);
  1209. /* HC Reset requires max 10 us delay */
  1210. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1211. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1212. if (--timeout == 0) {
  1213. err("USB HC reset timed out!");
  1214. return -1;
  1215. }
  1216. udelay (1);
  1217. }
  1218. return 0;
  1219. }
  1220. /*-------------------------------------------------------------------------*/
  1221. /* Start an OHCI controller, set the BUS operational
  1222. * enable interrupts
  1223. * connect the virtual root hub */
  1224. static int hc_start (ohci_t * ohci)
  1225. {
  1226. __u32 mask;
  1227. unsigned int fminterval;
  1228. ohci->disabled = 1;
  1229. /* Tell the controller where the control and bulk lists are
  1230. * The lists are empty now. */
  1231. writel (0, &ohci->regs->ed_controlhead);
  1232. writel (0, &ohci->regs->ed_bulkhead);
  1233. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1234. fminterval = 0x2edf;
  1235. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1236. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1237. writel (fminterval, &ohci->regs->fminterval);
  1238. writel (0x628, &ohci->regs->lsthresh);
  1239. /* start controller operations */
  1240. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1241. ohci->disabled = 0;
  1242. writel (ohci->hc_control, &ohci->regs->control);
  1243. /* disable all interrupts */
  1244. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1245. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1246. OHCI_INTR_OC | OHCI_INTR_MIE);
  1247. writel (mask, &ohci->regs->intrdisable);
  1248. /* clear all interrupts */
  1249. mask &= ~OHCI_INTR_MIE;
  1250. writel (mask, &ohci->regs->intrstatus);
  1251. /* Choose the interrupts we care about now - but w/o MIE */
  1252. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1253. writel (mask, &ohci->regs->intrenable);
  1254. #ifdef OHCI_USE_NPS
  1255. /* required for AMD-756 and some Mac platforms */
  1256. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1257. &ohci->regs->roothub.a);
  1258. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1259. #endif /* OHCI_USE_NPS */
  1260. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1261. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1262. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1263. /* connect the virtual root hub */
  1264. ohci->rh.devnum = 0;
  1265. return 0;
  1266. }
  1267. /*-------------------------------------------------------------------------*/
  1268. /* an interrupt happens */
  1269. static int
  1270. hc_interrupt (void)
  1271. {
  1272. ohci_t *ohci = &gohci;
  1273. struct ohci_regs *regs = ohci->regs;
  1274. int ints;
  1275. int stat = -1;
  1276. if ((ohci->hcca->done_head != 0) &&
  1277. !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
  1278. ints = OHCI_INTR_WDH;
  1279. } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
  1280. ohci->disabled++;
  1281. err ("%s device removed!", ohci->slot_name);
  1282. return -1;
  1283. } else if ((ints &= readl (&regs->intrenable)) == 0) {
  1284. dbg("hc_interrupt: returning..\n");
  1285. return 0xff;
  1286. }
  1287. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1288. if (ints & OHCI_INTR_RHSC) {
  1289. got_rhsc = 1;
  1290. stat = 0xff;
  1291. }
  1292. if (ints & OHCI_INTR_UE) {
  1293. ohci->disabled++;
  1294. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1295. ohci->slot_name);
  1296. /* e.g. due to PCI Master/Target Abort */
  1297. #ifdef DEBUG
  1298. ohci_dump (ohci, 1);
  1299. #endif
  1300. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1301. /* Make some non-interrupt context restart the controller. */
  1302. /* Count and limit the retries though; either hardware or */
  1303. /* software errors can go forever... */
  1304. hc_reset (ohci);
  1305. return -1;
  1306. }
  1307. if (ints & OHCI_INTR_WDH) {
  1308. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1309. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1310. writel (OHCI_INTR_WDH, &regs->intrenable);
  1311. }
  1312. if (ints & OHCI_INTR_SO) {
  1313. dbg("USB Schedule overrun\n");
  1314. writel (OHCI_INTR_SO, &regs->intrenable);
  1315. stat = -1;
  1316. }
  1317. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1318. if (ints & OHCI_INTR_SF) {
  1319. unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
  1320. wait_ms(1);
  1321. writel (OHCI_INTR_SF, &regs->intrdisable);
  1322. if (ohci->ed_rm_list[frame] != NULL)
  1323. writel (OHCI_INTR_SF, &regs->intrenable);
  1324. stat = 0xff;
  1325. }
  1326. writel (ints, &regs->intrstatus);
  1327. return stat;
  1328. }
  1329. /*-------------------------------------------------------------------------*/
  1330. /*-------------------------------------------------------------------------*/
  1331. /* De-allocate all resources.. */
  1332. static void hc_release_ohci (ohci_t *ohci)
  1333. {
  1334. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1335. if (!ohci->disabled)
  1336. hc_reset (ohci);
  1337. }
  1338. /*-------------------------------------------------------------------------*/
  1339. /*
  1340. * low level initalisation routine, called from usb.c
  1341. */
  1342. static char ohci_inited = 0;
  1343. int usb_lowlevel_init(void)
  1344. {
  1345. /* Set the USB Clock */
  1346. *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
  1347. /* remove all USB bits first before ORing in ours */
  1348. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
  1349. /* Activate USB port */
  1350. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
  1351. memset (&gohci, 0, sizeof (ohci_t));
  1352. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1353. /* align the storage */
  1354. if ((__u32)&ghcca[0] & 0xff) {
  1355. err("HCCA not aligned!!");
  1356. return -1;
  1357. }
  1358. phcca = &ghcca[0];
  1359. info("aligned ghcca %p", phcca);
  1360. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1361. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1362. err("EDs not aligned!!");
  1363. return -1;
  1364. }
  1365. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1366. if ((__u32)gtd & 0x7) {
  1367. err("TDs not aligned!!");
  1368. return -1;
  1369. }
  1370. ptd = gtd;
  1371. gohci.hcca = phcca;
  1372. memset (phcca, 0, sizeof (struct ohci_hcca));
  1373. gohci.disabled = 1;
  1374. gohci.sleeping = 0;
  1375. gohci.irq = -1;
  1376. gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
  1377. gohci.flags = 0;
  1378. gohci.slot_name = "mpc5200";
  1379. if (hc_reset (&gohci) < 0) {
  1380. hc_release_ohci (&gohci);
  1381. return -1;
  1382. }
  1383. if (hc_start (&gohci) < 0) {
  1384. err ("can't start usb-%s", gohci.slot_name);
  1385. hc_release_ohci (&gohci);
  1386. return -1;
  1387. }
  1388. #ifdef DEBUG
  1389. ohci_dump (&gohci, 1);
  1390. #endif
  1391. ohci_inited = 1;
  1392. urb_finished = 1;
  1393. return 0;
  1394. }
  1395. int usb_lowlevel_stop(void)
  1396. {
  1397. /* this gets called really early - before the controller has */
  1398. /* even been initialized! */
  1399. if (!ohci_inited)
  1400. return 0;
  1401. /* TODO release any interrupts, etc. */
  1402. /* call hc_release_ohci() here ? */
  1403. hc_reset (&gohci);
  1404. return 0;
  1405. }
  1406. #endif /* CONFIG_USB_OHCI */