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mx28evk
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iomux.c

iomux.c 6.8 KB
Cronologia Originale

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  1. /*
    2. 

  2.  * Freescale MX28EVK IOMUX setup
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
    5. 

  5.  * on behalf of DENX Software Engineering GmbH
    6. 

  6.  *
    7. 

  7.  * See file CREDITS for list of people who contributed to this
    8. 

  8.  * project.
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or
    11. 

  11.  * modify it under the terms of the GNU General Public License as
    12. 

  12.  * published by the Free Software Foundation; either version 2 of
    13. 

  13.  * the License, or (at your option) any later version.
    14. 

  14.  *
    15. 

  15.  * This program is distributed in the hope that it will be useful,
    16. 

  16.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17. 

  17.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18. 

  18.  * GNU General Public License for more details.
    19. 

  19.  */
    20. 

  20. 

  21. #include <common.h>
    22. 

  22. #include <config.h>
    23. 

  23. #include <asm/io.h>
    24. 

  24. #include <asm/arch/iomux-mx28.h>
    25. 

  25. #include <asm/arch/imx-regs.h>
    26. 

  26. #include <asm/arch/sys_proto.h>
    27. 

  27. 

  28. #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
    29. 

  29. #define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
    30. 

  30. #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
    31. 

  31. #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
    32. 

  32. #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
    33. 

  33. 

  34. const iomux_cfg_t iomux_setup[] = {
    35. 

  35. 	/* DUART */
    36. 

  36. 	MX28_PAD_PWM0__DUART_RX,
    37. 

  37. 	MX28_PAD_PWM1__DUART_TX,
    38. 

  38. 

  39. 	/* MMC0 */
    40. 

  40. 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
    41. 

  41. 	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
    42. 

  42. 	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
    43. 

  43. 	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
    44. 

  44. 	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
    45. 

  45. 	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
    46. 

  46. 	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
    47. 

  47. 	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
    48. 

  48. 	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
    49. 

  49. 	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
    50. 

  50. 		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
    51. 

  51. 	MX28_PAD_SSP0_SCK__SSP0_SCK |
    52. 

  52. 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
    53. 

  53. 	/* write protect */
    54. 

  54. 	MX28_PAD_SSP1_SCK__GPIO_2_12,
    55. 

  55. 	/* MMC0 slot power enable */
    56. 

  56. 	MX28_PAD_PWM3__GPIO_3_28 |
    57. 

  57. 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
    58. 

  58. 

  59. #ifdef CONFIG_NAND_MXS
    60. 

  60. 	/* GPMI NAND */
    61. 

  61. 	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
    62. 

  62. 	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
    63. 

  63. 	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
    64. 

  64. 	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
    65. 

  65. 	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
    66. 

  66. 	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
    67. 

  67. 	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
    68. 

  68. 	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
    69. 

  69. 	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
    70. 

  70. 	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
    71. 

  71. 	MX28_PAD_GPMI_RDN__GPMI_RDN |
    72. 

  72. 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
    73. 

  73. 	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
    74. 

  74. 	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
    75. 

  75. 	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
    76. 

  76. 	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
    77. 

  77. #endif
    78. 

  78. 

  79. 	/* FEC0 */
    80. 

  80. 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
    81. 

  81. 	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
    82. 

  82. 	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
    83. 

  83. 	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
    84. 

  84. 	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
    85. 

  85. 	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
    86. 

  86. 	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
    87. 

  87. 	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
    88. 

  88. 	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
    89. 

  89. 	/* FEC0 Enable */
    90. 

  90. 	MX28_PAD_SSP1_DATA3__GPIO_2_15 |
    91. 

  91. 		(MXS_PAD_12MA | MXS_PAD_3V3),
    92. 

  92. 	/* FEC0 Reset */
    93. 

  93. 	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
    94. 

  94. 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
    95. 

  95. 

  96. 	/* FEC1 */
    97. 

  97. 	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
    98. 

  98. 	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
    99. 

  99. 	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
    100. 

  100. 	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
    101. 

  101. 	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
    102. 

  102. 	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
    103. 

  103. 

  104. 	/* EMI */
    105. 

  105. 	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
    106. 

  106. 	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
    107. 

  107. 	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
    108. 

  108. 	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
    109. 

  109. 	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
    110. 

  110. 	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
    111. 

  111. 	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
    112. 

  112. 	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
    113. 

  113. 	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
    114. 

  114. 	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
    115. 

  115. 	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
    116. 

  116. 	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
    117. 

  117. 	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
    118. 

  118. 	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
    119. 

  119. 	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
    120. 

  120. 	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
    121. 

  121. 	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
    122. 

  122. 	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
    123. 

  123. 	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
    124. 

  124. 	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
    125. 

  125. 	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
    126. 

  126. 	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
    127. 

  127. 	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
    128. 

  128. 	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
    129. 

  129. 	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
    130. 

  130. 

  131. 	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
    132. 

  132. 	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
    133. 

  133. 	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
    134. 

  134. 	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
    135. 

  135. 	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
    136. 

  136. 	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
    137. 

  137. 	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
    138. 

  138. 	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
    139. 

  139. 	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
    140. 

  140. 	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
    141. 

  141. 	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
    142. 

  142. 	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
    143. 

  143. 	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
    144. 

  144. 	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
    145. 

  145. 	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
    146. 

  146. 	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
    147. 

  147. 	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
    148. 

  148. 	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
    149. 

  149. 	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
    150. 

  150. 	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
    151. 

  151. 	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
    152. 

  152. 	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
    153. 

  153. 	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
    154. 

  154. 	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
    155. 

  155. 

  156. 	/* SPI2 (for SPI flash) */
    157. 

  157. 	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
    158. 

  158. 	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
    159. 

  159. 	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
    160. 

  160. 	MX28_PAD_SSP2_SS0__SSP2_D3 |
    161. 

  161. 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
    162. 

  162. 	/* I2C */
    163. 

  163. 	MX28_PAD_I2C0_SCL__I2C0_SCL,
    164. 

  164. 	MX28_PAD_I2C0_SDA__I2C0_SDA,
    165. 

  165. };
    166. 

  166. 

  167. #define HW_DRAM_CTL29	(0x74 >> 2)
    168. 

  168. #define CS_MAP		0xf
    169. 

  169. #define COLUMN_SIZE	0x2
    170. 

  170. #define ADDR_PINS	0x1
    171. 

  171. #define APREBIT		0xa
    172. 

  172. 

  173. #define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
    174. 

  174. 					ADDR_PINS << 8 | APREBIT)
    175. 

  175. 

  176. void mxs_adjust_memory_params(uint32_t *dram_vals)
    177. 

  177. {
    178. 

  178. 	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
    179. 

  179. }
    180. 

  180. 

  181. void board_init_ll(void)
    182. 

  182. {
    183. 

  183. 	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
    184. 

  184. }
    185.