usb_ohci.c 46 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * Note: Much of this code has been derived from Linux 2.4
  8. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  9. * (C) Copyright 2000-2002 David Brownell
  10. *
  11. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  12. * ebenard@eukrea.com - based on s3c24x0's driver
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - you MUST define LITTLEENDIAN in the configuration file for the
  36. * board or this driver will NOT work!
  37. * 2 - this driver is intended for use with USB Mass Storage Devices
  38. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  39. * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  40. * to activate workaround for bug #41 or this driver will NOT work!
  41. */
  42. #include <common.h>
  43. /* #include <pci.h> no PCI on the S3C24X0 */
  44. #ifdef CONFIG_USB_OHCI
  45. #if defined(CONFIG_S3C2400)
  46. # include <s3c2400.h>
  47. #elif defined(CONFIG_S3C2410)
  48. # include <s3c2410.h>
  49. #elif defined(CONFIG_ARM920T)
  50. # include <asm/arch/hardware.h>
  51. #elif defined(CONFIG_CPU_MONAHANS)
  52. # include <asm/arch/pxa-regs.h>
  53. #endif
  54. #include <malloc.h>
  55. #include <usb.h>
  56. #include "usb_ohci.h"
  57. #undef S3C24X0_merge
  58. #if defined(CONFIG_ARM920T) || \
  59. defined(CONFIG_S3C2400) || \
  60. defined(CONFIG_S3C2410)
  61. # define OHCI_USE_NPS /* force NoPowerSwitching mode */
  62. #endif
  63. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  64. /* For initializing controller (mask in an HCFS mode too) */
  65. #define OHCI_CONTROL_INIT \
  66. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  67. #define readl(a) (*((vu_long *)(a)))
  68. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  69. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  70. #undef DEBUG
  71. #ifdef DEBUG
  72. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  73. #else
  74. #define dbg(format, arg...) do {} while(0)
  75. #endif /* DEBUG */
  76. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  77. #undef SHOW_INFO
  78. #ifdef SHOW_INFO
  79. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  80. #else
  81. #define info(format, arg...) do {} while(0)
  82. #endif
  83. #define m16_swap(x) swap_16(x)
  84. #define m32_swap(x) swap_32(x)
  85. /* global ohci_t */
  86. static ohci_t gohci;
  87. /* this must be aligned to a 256 byte boundary */
  88. struct ohci_hcca ghcca[1];
  89. /* a pointer to the aligned storage */
  90. struct ohci_hcca *phcca;
  91. /* this allocates EDs for all possible endpoints */
  92. struct ohci_device ohci_dev;
  93. /* urb_priv */
  94. urb_priv_t urb_priv;
  95. /* RHSC flag */
  96. int got_rhsc;
  97. /* device which was disconnected */
  98. struct usb_device *devgone;
  99. #ifdef S3C24X0_merge
  100. /* flag guarding URB transation */
  101. int urb_finished = 0;
  102. #endif
  103. /*-------------------------------------------------------------------------*/
  104. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  105. * The erratum (#4) description is incorrect. AMD's workaround waits
  106. * till some bits (mostly reserved) are clear; ok for all revs.
  107. */
  108. #define OHCI_QUIRK_AMD756 0xabcd
  109. #define read_roothub(hc, register, mask) ({ \
  110. u32 temp = readl (&hc->regs->roothub.register); \
  111. if (hc->flags & OHCI_QUIRK_AMD756) \
  112. while (temp & mask) \
  113. temp = readl (&hc->regs->roothub.register); \
  114. temp; })
  115. static u32 roothub_a (struct ohci *hc)
  116. { return read_roothub (hc, a, 0xfc0fe000); }
  117. static inline u32 roothub_b (struct ohci *hc)
  118. { return readl (&hc->regs->roothub.b); }
  119. static inline u32 roothub_status (struct ohci *hc)
  120. { return readl (&hc->regs->roothub.status); }
  121. static u32 roothub_portstatus (struct ohci *hc, int i)
  122. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  123. /* forward declaration */
  124. static int hc_interrupt (void);
  125. static void
  126. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  127. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  128. /*-------------------------------------------------------------------------*
  129. * URB support functions
  130. *-------------------------------------------------------------------------*/
  131. /* free HCD-private data associated with this URB */
  132. static void urb_free_priv (urb_priv_t * urb)
  133. {
  134. int i;
  135. int last;
  136. struct td * td;
  137. last = urb->length - 1;
  138. if (last >= 0) {
  139. for (i = 0; i <= last; i++) {
  140. td = urb->td[i];
  141. if (td) {
  142. td->usb_dev = NULL;
  143. urb->td[i] = NULL;
  144. }
  145. }
  146. }
  147. }
  148. /*-------------------------------------------------------------------------*/
  149. #ifdef DEBUG
  150. static int sohci_get_current_frame_number (struct usb_device * dev);
  151. /* debug| print the main components of an URB
  152. * small: 0) header + data packets 1) just header */
  153. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  154. int transfer_len, struct devrequest * setup, char * str, int small)
  155. {
  156. urb_priv_t * purb = &urb_priv;
  157. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  158. str,
  159. sohci_get_current_frame_number (dev),
  160. usb_pipedevice (pipe),
  161. usb_pipeendpoint (pipe),
  162. usb_pipeout (pipe)? 'O': 'I',
  163. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  164. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  165. purb->actual_length,
  166. transfer_len, dev->status);
  167. #ifdef OHCI_VERBOSE_DEBUG
  168. if (!small) {
  169. int i, len;
  170. if (usb_pipecontrol (pipe)) {
  171. printf (__FILE__ ": cmd(8):");
  172. for (i = 0; i < 8 ; i++)
  173. printf (" %02x", ((__u8 *) setup) [i]);
  174. printf ("\n");
  175. }
  176. if (transfer_len > 0 && buffer) {
  177. printf (__FILE__ ": data(%d/%d):",
  178. purb->actual_length,
  179. transfer_len);
  180. len = usb_pipeout (pipe)?
  181. transfer_len: purb->actual_length;
  182. for (i = 0; i < 16 && i < len; i++)
  183. printf (" %02x", ((__u8 *) buffer) [i]);
  184. printf ("%s\n", i < len? "...": "");
  185. }
  186. }
  187. #endif
  188. }
  189. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  190. void ep_print_int_eds (ohci_t *ohci, char * str) {
  191. int i, j;
  192. __u32 * ed_p;
  193. for (i= 0; i < 32; i++) {
  194. j = 5;
  195. ed_p = &(ohci->hcca->int_table [i]);
  196. if (*ed_p == 0)
  197. continue;
  198. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  199. while (*ed_p != 0 && j--) {
  200. ed_t *ed = (ed_t *)m32_swap(ed_p);
  201. printf (" ed: %4x;", ed->hwINFO);
  202. ed_p = &ed->hwNextED;
  203. }
  204. printf ("\n");
  205. }
  206. }
  207. static void ohci_dump_intr_mask (char *label, __u32 mask)
  208. {
  209. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  210. label,
  211. mask,
  212. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  213. (mask & OHCI_INTR_OC) ? " OC" : "",
  214. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  215. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  216. (mask & OHCI_INTR_UE) ? " UE" : "",
  217. (mask & OHCI_INTR_RD) ? " RD" : "",
  218. (mask & OHCI_INTR_SF) ? " SF" : "",
  219. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  220. (mask & OHCI_INTR_SO) ? " SO" : ""
  221. );
  222. }
  223. static void maybe_print_eds (char *label, __u32 value)
  224. {
  225. ed_t *edp = (ed_t *)value;
  226. if (value) {
  227. dbg ("%s %08x", label, value);
  228. dbg ("%08x", edp->hwINFO);
  229. dbg ("%08x", edp->hwTailP);
  230. dbg ("%08x", edp->hwHeadP);
  231. dbg ("%08x", edp->hwNextED);
  232. }
  233. }
  234. static char * hcfs2string (int state)
  235. {
  236. switch (state) {
  237. case OHCI_USB_RESET: return "reset";
  238. case OHCI_USB_RESUME: return "resume";
  239. case OHCI_USB_OPER: return "operational";
  240. case OHCI_USB_SUSPEND: return "suspend";
  241. }
  242. return "?";
  243. }
  244. /* dump control and status registers */
  245. static void ohci_dump_status (ohci_t *controller)
  246. {
  247. struct ohci_regs *regs = controller->regs;
  248. __u32 temp;
  249. temp = readl (&regs->revision) & 0xff;
  250. if (temp != 0x10)
  251. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  252. temp = readl (&regs->control);
  253. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  254. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  255. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  256. (temp & OHCI_CTRL_IR) ? " IR" : "",
  257. hcfs2string (temp & OHCI_CTRL_HCFS),
  258. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  259. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  260. (temp & OHCI_CTRL_IE) ? " IE" : "",
  261. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  262. temp & OHCI_CTRL_CBSR
  263. );
  264. temp = readl (&regs->cmdstatus);
  265. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  266. (temp & OHCI_SOC) >> 16,
  267. (temp & OHCI_OCR) ? " OCR" : "",
  268. (temp & OHCI_BLF) ? " BLF" : "",
  269. (temp & OHCI_CLF) ? " CLF" : "",
  270. (temp & OHCI_HCR) ? " HCR" : ""
  271. );
  272. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  273. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  274. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  275. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  276. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  277. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  278. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  279. maybe_print_eds ("donehead", readl (&regs->donehead));
  280. }
  281. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  282. {
  283. __u32 temp, ndp, i;
  284. temp = roothub_a (controller);
  285. ndp = (temp & RH_A_NDP);
  286. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  287. ndp = (ndp == 2) ? 1:0;
  288. #endif
  289. if (verbose) {
  290. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  291. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  292. (temp & RH_A_NOCP) ? " NOCP" : "",
  293. (temp & RH_A_OCPM) ? " OCPM" : "",
  294. (temp & RH_A_DT) ? " DT" : "",
  295. (temp & RH_A_NPS) ? " NPS" : "",
  296. (temp & RH_A_PSM) ? " PSM" : "",
  297. ndp
  298. );
  299. temp = roothub_b (controller);
  300. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  301. temp,
  302. (temp & RH_B_PPCM) >> 16,
  303. (temp & RH_B_DR)
  304. );
  305. temp = roothub_status (controller);
  306. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  307. temp,
  308. (temp & RH_HS_CRWE) ? " CRWE" : "",
  309. (temp & RH_HS_OCIC) ? " OCIC" : "",
  310. (temp & RH_HS_LPSC) ? " LPSC" : "",
  311. (temp & RH_HS_DRWE) ? " DRWE" : "",
  312. (temp & RH_HS_OCI) ? " OCI" : "",
  313. (temp & RH_HS_LPS) ? " LPS" : ""
  314. );
  315. }
  316. for (i = 0; i < ndp; i++) {
  317. temp = roothub_portstatus (controller, i);
  318. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  319. i,
  320. temp,
  321. (temp & RH_PS_PRSC) ? " PRSC" : "",
  322. (temp & RH_PS_OCIC) ? " OCIC" : "",
  323. (temp & RH_PS_PSSC) ? " PSSC" : "",
  324. (temp & RH_PS_PESC) ? " PESC" : "",
  325. (temp & RH_PS_CSC) ? " CSC" : "",
  326. (temp & RH_PS_LSDA) ? " LSDA" : "",
  327. (temp & RH_PS_PPS) ? " PPS" : "",
  328. (temp & RH_PS_PRS) ? " PRS" : "",
  329. (temp & RH_PS_POCI) ? " POCI" : "",
  330. (temp & RH_PS_PSS) ? " PSS" : "",
  331. (temp & RH_PS_PES) ? " PES" : "",
  332. (temp & RH_PS_CCS) ? " CCS" : ""
  333. );
  334. }
  335. }
  336. static void ohci_dump (ohci_t *controller, int verbose)
  337. {
  338. dbg ("OHCI controller usb-%s state", controller->slot_name);
  339. /* dumps some of the state we know about */
  340. ohci_dump_status (controller);
  341. if (verbose)
  342. ep_print_int_eds (controller, "hcca");
  343. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  344. ohci_dump_roothub (controller, 1);
  345. }
  346. #endif /* DEBUG */
  347. /*-------------------------------------------------------------------------*
  348. * Interface functions (URB)
  349. *-------------------------------------------------------------------------*/
  350. /* get a transfer request */
  351. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  352. int transfer_len, struct devrequest *setup, int interval)
  353. {
  354. ohci_t *ohci;
  355. ed_t * ed;
  356. urb_priv_t *purb_priv;
  357. int i, size = 0;
  358. ohci = &gohci;
  359. /* when controller's hung, permit only roothub cleanup attempts
  360. * such as powering down ports */
  361. if (ohci->disabled) {
  362. err("sohci_submit_job: EPIPE");
  363. return -1;
  364. }
  365. #ifdef S3C24X0_merge
  366. /* if we have an unfinished URB from previous transaction let's
  367. * fail and scream as quickly as possible so as not to corrupt
  368. * further communication */
  369. if (!urb_finished) {
  370. err("sohci_submit_job: URB NOT FINISHED");
  371. return -1;
  372. }
  373. /* we're about to begin a new transaction here so mark the URB unfinished */
  374. urb_finished = 0;
  375. #endif
  376. /* every endpoint has a ed, locate and fill it */
  377. if (!(ed = ep_add_ed (dev, pipe))) {
  378. err("sohci_submit_job: ENOMEM");
  379. return -1;
  380. }
  381. /* for the private part of the URB we need the number of TDs (size) */
  382. switch (usb_pipetype (pipe)) {
  383. case PIPE_BULK: /* one TD for every 4096 Byte */
  384. size = (transfer_len - 1) / 4096 + 1;
  385. break;
  386. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  387. size = (transfer_len == 0)? 2:
  388. (transfer_len - 1) / 4096 + 3;
  389. break;
  390. }
  391. if (size >= (N_URB_TD - 1)) {
  392. err("need %d TDs, only have %d", size, N_URB_TD);
  393. return -1;
  394. }
  395. purb_priv = &urb_priv;
  396. purb_priv->pipe = pipe;
  397. /* fill the private part of the URB */
  398. purb_priv->length = size;
  399. purb_priv->ed = ed;
  400. purb_priv->actual_length = 0;
  401. /* allocate the TDs */
  402. /* note that td[0] was allocated in ep_add_ed */
  403. for (i = 0; i < size; i++) {
  404. purb_priv->td[i] = td_alloc (dev);
  405. if (!purb_priv->td[i]) {
  406. purb_priv->length = i;
  407. urb_free_priv (purb_priv);
  408. err("sohci_submit_job: ENOMEM");
  409. return -1;
  410. }
  411. }
  412. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  413. urb_free_priv (purb_priv);
  414. err("sohci_submit_job: EINVAL");
  415. return -1;
  416. }
  417. /* link the ed into a chain if is not already */
  418. if (ed->state != ED_OPER)
  419. ep_link (ohci, ed);
  420. /* fill the TDs and link it to the ed */
  421. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  422. return 0;
  423. }
  424. /*-------------------------------------------------------------------------*/
  425. #ifdef DEBUG
  426. /* tell us the current USB frame number */
  427. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  428. {
  429. ohci_t *ohci = &gohci;
  430. return m16_swap (ohci->hcca->frame_no);
  431. }
  432. #endif
  433. /*-------------------------------------------------------------------------*
  434. * ED handling functions
  435. *-------------------------------------------------------------------------*/
  436. /* link an ed into one of the HC chains */
  437. static int ep_link (ohci_t *ohci, ed_t *edi)
  438. {
  439. volatile ed_t *ed = edi;
  440. ed->state = ED_OPER;
  441. switch (ed->type) {
  442. case PIPE_CONTROL:
  443. ed->hwNextED = 0;
  444. if (ohci->ed_controltail == NULL) {
  445. writel (ed, &ohci->regs->ed_controlhead);
  446. } else {
  447. ohci->ed_controltail->hwNextED = m32_swap (ed);
  448. }
  449. ed->ed_prev = ohci->ed_controltail;
  450. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  451. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  452. ohci->hc_control |= OHCI_CTRL_CLE;
  453. writel (ohci->hc_control, &ohci->regs->control);
  454. }
  455. ohci->ed_controltail = edi;
  456. break;
  457. case PIPE_BULK:
  458. ed->hwNextED = 0;
  459. if (ohci->ed_bulktail == NULL) {
  460. writel (ed, &ohci->regs->ed_bulkhead);
  461. } else {
  462. ohci->ed_bulktail->hwNextED = m32_swap (ed);
  463. }
  464. ed->ed_prev = ohci->ed_bulktail;
  465. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  466. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  467. ohci->hc_control |= OHCI_CTRL_BLE;
  468. writel (ohci->hc_control, &ohci->regs->control);
  469. }
  470. ohci->ed_bulktail = edi;
  471. break;
  472. }
  473. return 0;
  474. }
  475. /*-------------------------------------------------------------------------*/
  476. /* unlink an ed from one of the HC chains.
  477. * just the link to the ed is unlinked.
  478. * the link from the ed still points to another operational ed or 0
  479. * so the HC can eventually finish the processing of the unlinked ed */
  480. static int ep_unlink (ohci_t *ohci, ed_t *ed)
  481. {
  482. ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
  483. switch (ed->type) {
  484. case PIPE_CONTROL:
  485. if (ed->ed_prev == NULL) {
  486. if (!ed->hwNextED) {
  487. ohci->hc_control &= ~OHCI_CTRL_CLE;
  488. writel (ohci->hc_control, &ohci->regs->control);
  489. }
  490. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  491. } else {
  492. ed->ed_prev->hwNextED = ed->hwNextED;
  493. }
  494. if (ohci->ed_controltail == ed) {
  495. ohci->ed_controltail = ed->ed_prev;
  496. } else {
  497. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  498. }
  499. break;
  500. case PIPE_BULK:
  501. if (ed->ed_prev == NULL) {
  502. if (!ed->hwNextED) {
  503. ohci->hc_control &= ~OHCI_CTRL_BLE;
  504. writel (ohci->hc_control, &ohci->regs->control);
  505. }
  506. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  507. } else {
  508. ed->ed_prev->hwNextED = ed->hwNextED;
  509. }
  510. if (ohci->ed_bulktail == ed) {
  511. ohci->ed_bulktail = ed->ed_prev;
  512. } else {
  513. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  514. }
  515. break;
  516. }
  517. ed->state = ED_UNLINK;
  518. return 0;
  519. }
  520. /*-------------------------------------------------------------------------*/
  521. /* add/reinit an endpoint; this should be done once at the
  522. * usb_set_configuration command, but the USB stack is a little bit
  523. * stateless so we do it at every transaction if the state of the ed
  524. * is ED_NEW then a dummy td is added and the state is changed to
  525. * ED_UNLINK in all other cases the state is left unchanged the ed
  526. * info fields are setted anyway even though most of them should not
  527. * change
  528. */
  529. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  530. {
  531. td_t *td;
  532. ed_t *ed_ret;
  533. volatile ed_t *ed;
  534. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  535. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  536. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  537. err("ep_add_ed: pending delete");
  538. /* pending delete request */
  539. return NULL;
  540. }
  541. if (ed->state == ED_NEW) {
  542. ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
  543. /* dummy td; end of td list for ed */
  544. td = td_alloc (usb_dev);
  545. ed->hwTailP = m32_swap (td);
  546. ed->hwHeadP = ed->hwTailP;
  547. ed->state = ED_UNLINK;
  548. ed->type = usb_pipetype (pipe);
  549. ohci_dev.ed_cnt++;
  550. }
  551. ed->hwINFO = m32_swap (usb_pipedevice (pipe)
  552. | usb_pipeendpoint (pipe) << 7
  553. | (usb_pipeisoc (pipe)? 0x8000: 0)
  554. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  555. | usb_pipeslow (pipe) << 13
  556. | usb_maxpacket (usb_dev, pipe) << 16);
  557. return ed_ret;
  558. }
  559. /*-------------------------------------------------------------------------*
  560. * TD handling functions
  561. *-------------------------------------------------------------------------*/
  562. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  563. static void td_fill (ohci_t *ohci, unsigned int info,
  564. void *data, int len,
  565. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  566. {
  567. volatile td_t *td, *td_pt;
  568. #ifdef OHCI_FILL_TRACE
  569. int i;
  570. #endif
  571. if (index > urb_priv->length) {
  572. err("index > length");
  573. return;
  574. }
  575. /* use this td as the next dummy */
  576. td_pt = urb_priv->td [index];
  577. td_pt->hwNextTD = 0;
  578. /* fill the old dummy TD */
  579. td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
  580. td->ed = urb_priv->ed;
  581. td->next_dl_td = NULL;
  582. td->index = index;
  583. td->data = (__u32)data;
  584. #ifdef OHCI_FILL_TRACE
  585. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  586. for (i = 0; i < len; i++)
  587. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  588. printf("\n");
  589. }
  590. #endif
  591. if (!len)
  592. data = 0;
  593. td->hwINFO = m32_swap (info);
  594. td->hwCBP = m32_swap (data);
  595. if (data)
  596. td->hwBE = m32_swap (data + len - 1);
  597. else
  598. td->hwBE = 0;
  599. td->hwNextTD = m32_swap (td_pt);
  600. #ifndef S3C24X0_merge
  601. td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
  602. #endif
  603. /* append to queue */
  604. td->ed->hwTailP = td->hwNextTD;
  605. }
  606. /*-------------------------------------------------------------------------*/
  607. /* prepare all TDs of a transfer */
  608. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  609. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  610. {
  611. ohci_t *ohci = &gohci;
  612. int data_len = transfer_len;
  613. void *data;
  614. int cnt = 0;
  615. __u32 info = 0;
  616. unsigned int toggle = 0;
  617. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  618. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  619. toggle = TD_T_TOGGLE;
  620. } else {
  621. toggle = TD_T_DATA0;
  622. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  623. }
  624. urb->td_cnt = 0;
  625. if (data_len)
  626. data = buffer;
  627. else
  628. data = 0;
  629. switch (usb_pipetype (pipe)) {
  630. case PIPE_BULK:
  631. info = usb_pipeout (pipe)?
  632. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  633. while(data_len > 4096) {
  634. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  635. data += 4096; data_len -= 4096; cnt++;
  636. }
  637. info = usb_pipeout (pipe)?
  638. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  639. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  640. cnt++;
  641. if (!ohci->sleeping)
  642. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  643. break;
  644. case PIPE_CONTROL:
  645. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  646. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  647. if (data_len > 0) {
  648. info = usb_pipeout (pipe)?
  649. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  650. /* NOTE: mishandles transfers >8K, some >4K */
  651. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  652. }
  653. info = usb_pipeout (pipe)?
  654. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  655. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  656. if (!ohci->sleeping)
  657. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  658. break;
  659. }
  660. if (urb->length != cnt)
  661. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  662. }
  663. /*-------------------------------------------------------------------------*
  664. * Done List handling functions
  665. *-------------------------------------------------------------------------*/
  666. /* calculate the transfer length and update the urb */
  667. static void dl_transfer_length(td_t * td)
  668. {
  669. __u32 tdINFO, tdBE, tdCBP;
  670. urb_priv_t *lurb_priv = &urb_priv;
  671. tdINFO = m32_swap (td->hwINFO);
  672. tdBE = m32_swap (td->hwBE);
  673. tdCBP = m32_swap (td->hwCBP);
  674. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  675. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  676. if (tdBE != 0) {
  677. if (td->hwCBP == 0)
  678. lurb_priv->actual_length += tdBE - td->data + 1;
  679. else
  680. lurb_priv->actual_length += tdCBP - td->data;
  681. }
  682. }
  683. }
  684. /*-------------------------------------------------------------------------*/
  685. /* replies to the request have to be on a FIFO basis so
  686. * we reverse the reversed done-list */
  687. static td_t * dl_reverse_done_list (ohci_t *ohci)
  688. {
  689. __u32 td_list_hc;
  690. td_t *td_rev = NULL;
  691. td_t *td_list = NULL;
  692. urb_priv_t *lurb_priv = NULL;
  693. td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
  694. ohci->hcca->done_head = 0;
  695. while (td_list_hc) {
  696. td_list = (td_t *)td_list_hc;
  697. if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
  698. lurb_priv = &urb_priv;
  699. dbg(" USB-error/status: %x : %p",
  700. TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
  701. if (td_list->ed->hwHeadP & m32_swap (0x1)) {
  702. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  703. td_list->ed->hwHeadP =
  704. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
  705. (td_list->ed->hwHeadP & m32_swap (0x2));
  706. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  707. } else
  708. td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
  709. }
  710. }
  711. td_list->next_dl_td = td_rev;
  712. td_rev = td_list;
  713. td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
  714. }
  715. return td_list;
  716. }
  717. /*-------------------------------------------------------------------------*/
  718. /* td done list */
  719. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  720. {
  721. td_t *td_list_next = NULL;
  722. ed_t *ed;
  723. int cc = 0;
  724. int stat = 0;
  725. /* urb_t *urb; */
  726. urb_priv_t *lurb_priv;
  727. __u32 tdINFO, edHeadP, edTailP;
  728. while (td_list) {
  729. td_list_next = td_list->next_dl_td;
  730. lurb_priv = &urb_priv;
  731. tdINFO = m32_swap (td_list->hwINFO);
  732. ed = td_list->ed;
  733. dl_transfer_length(td_list);
  734. /* error code of transfer */
  735. cc = TD_CC_GET (tdINFO);
  736. if (cc != 0) {
  737. dbg("ConditionCode %#x", cc);
  738. stat = cc_to_error[cc];
  739. }
  740. #ifdef S3C24X0_merge
  741. /* see if this done list makes for all TD's of current URB,
  742. * and mark the URB finished if so */
  743. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  744. if ((ed->state & (ED_OPER | ED_UNLINK)))
  745. urb_finished = 1;
  746. else
  747. dbg("dl_done_list: strange.., ED state %x, ed->state\n");
  748. } else
  749. dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
  750. lurb_priv->length);
  751. #endif
  752. if (ed->state != ED_NEW) {
  753. edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
  754. edTailP = m32_swap (ed->hwTailP);
  755. /* unlink eds if they are not busy */
  756. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  757. ep_unlink (ohci, ed);
  758. }
  759. td_list = td_list_next;
  760. }
  761. return stat;
  762. }
  763. /*-------------------------------------------------------------------------*
  764. * Virtual Root Hub
  765. *-------------------------------------------------------------------------*/
  766. /* Device descriptor */
  767. static __u8 root_hub_dev_des[] =
  768. {
  769. 0x12, /* __u8 bLength; */
  770. 0x01, /* __u8 bDescriptorType; Device */
  771. 0x10, /* __u16 bcdUSB; v1.1 */
  772. 0x01,
  773. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  774. 0x00, /* __u8 bDeviceSubClass; */
  775. 0x00, /* __u8 bDeviceProtocol; */
  776. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  777. 0x00, /* __u16 idVendor; */
  778. 0x00,
  779. 0x00, /* __u16 idProduct; */
  780. 0x00,
  781. 0x00, /* __u16 bcdDevice; */
  782. 0x00,
  783. 0x00, /* __u8 iManufacturer; */
  784. 0x01, /* __u8 iProduct; */
  785. 0x00, /* __u8 iSerialNumber; */
  786. 0x01 /* __u8 bNumConfigurations; */
  787. };
  788. /* Configuration descriptor */
  789. static __u8 root_hub_config_des[] =
  790. {
  791. 0x09, /* __u8 bLength; */
  792. 0x02, /* __u8 bDescriptorType; Configuration */
  793. 0x19, /* __u16 wTotalLength; */
  794. 0x00,
  795. 0x01, /* __u8 bNumInterfaces; */
  796. 0x01, /* __u8 bConfigurationValue; */
  797. 0x00, /* __u8 iConfiguration; */
  798. 0x40, /* __u8 bmAttributes;
  799. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  800. 0x00, /* __u8 MaxPower; */
  801. /* interface */
  802. 0x09, /* __u8 if_bLength; */
  803. 0x04, /* __u8 if_bDescriptorType; Interface */
  804. 0x00, /* __u8 if_bInterfaceNumber; */
  805. 0x00, /* __u8 if_bAlternateSetting; */
  806. 0x01, /* __u8 if_bNumEndpoints; */
  807. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  808. 0x00, /* __u8 if_bInterfaceSubClass; */
  809. 0x00, /* __u8 if_bInterfaceProtocol; */
  810. 0x00, /* __u8 if_iInterface; */
  811. /* endpoint */
  812. 0x07, /* __u8 ep_bLength; */
  813. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  814. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  815. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  816. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  817. 0x00,
  818. 0xff /* __u8 ep_bInterval; 255 ms */
  819. };
  820. static unsigned char root_hub_str_index0[] =
  821. {
  822. 0x04, /* __u8 bLength; */
  823. 0x03, /* __u8 bDescriptorType; String-descriptor */
  824. 0x09, /* __u8 lang ID */
  825. 0x04, /* __u8 lang ID */
  826. };
  827. static unsigned char root_hub_str_index1[] =
  828. {
  829. 28, /* __u8 bLength; */
  830. 0x03, /* __u8 bDescriptorType; String-descriptor */
  831. 'O', /* __u8 Unicode */
  832. 0, /* __u8 Unicode */
  833. 'H', /* __u8 Unicode */
  834. 0, /* __u8 Unicode */
  835. 'C', /* __u8 Unicode */
  836. 0, /* __u8 Unicode */
  837. 'I', /* __u8 Unicode */
  838. 0, /* __u8 Unicode */
  839. ' ', /* __u8 Unicode */
  840. 0, /* __u8 Unicode */
  841. 'R', /* __u8 Unicode */
  842. 0, /* __u8 Unicode */
  843. 'o', /* __u8 Unicode */
  844. 0, /* __u8 Unicode */
  845. 'o', /* __u8 Unicode */
  846. 0, /* __u8 Unicode */
  847. 't', /* __u8 Unicode */
  848. 0, /* __u8 Unicode */
  849. ' ', /* __u8 Unicode */
  850. 0, /* __u8 Unicode */
  851. 'H', /* __u8 Unicode */
  852. 0, /* __u8 Unicode */
  853. 'u', /* __u8 Unicode */
  854. 0, /* __u8 Unicode */
  855. 'b', /* __u8 Unicode */
  856. 0, /* __u8 Unicode */
  857. };
  858. /* Hub class-specific descriptor is constructed dynamically */
  859. /*-------------------------------------------------------------------------*/
  860. #define OK(x) len = (x); break
  861. #ifdef DEBUG
  862. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  863. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  864. #else
  865. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  866. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  867. #endif
  868. #define RD_RH_STAT roothub_status(&gohci)
  869. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  870. /* request to virtual root hub */
  871. int rh_check_port_status(ohci_t *controller)
  872. {
  873. __u32 temp, ndp, i;
  874. int res;
  875. res = -1;
  876. temp = roothub_a (controller);
  877. ndp = (temp & RH_A_NDP);
  878. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  879. ndp = (ndp == 2) ? 1:0;
  880. #endif
  881. for (i = 0; i < ndp; i++) {
  882. temp = roothub_portstatus (controller, i);
  883. /* check for a device disconnect */
  884. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  885. (RH_PS_PESC | RH_PS_CSC)) &&
  886. ((temp & RH_PS_CCS) == 0)) {
  887. res = i;
  888. break;
  889. }
  890. }
  891. return res;
  892. }
  893. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  894. void *buffer, int transfer_len, struct devrequest *cmd)
  895. {
  896. void * data = buffer;
  897. int leni = transfer_len;
  898. int len = 0;
  899. int stat = 0;
  900. __u32 datab[4];
  901. __u8 *data_buf = (__u8 *)datab;
  902. __u16 bmRType_bReq;
  903. __u16 wValue;
  904. __u16 wIndex;
  905. __u16 wLength;
  906. #ifdef DEBUG
  907. urb_priv.actual_length = 0;
  908. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  909. #else
  910. wait_ms(1);
  911. #endif
  912. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  913. info("Root-Hub submit IRQ: NOT implemented");
  914. return 0;
  915. }
  916. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  917. wValue = m16_swap (cmd->value);
  918. wIndex = m16_swap (cmd->index);
  919. wLength = m16_swap (cmd->length);
  920. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  921. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  922. switch (bmRType_bReq) {
  923. /* Request Destination:
  924. without flags: Device,
  925. RH_INTERFACE: interface,
  926. RH_ENDPOINT: endpoint,
  927. RH_CLASS means HUB here,
  928. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  929. */
  930. case RH_GET_STATUS:
  931. *(__u16 *) data_buf = m16_swap (1); OK (2);
  932. case RH_GET_STATUS | RH_INTERFACE:
  933. *(__u16 *) data_buf = m16_swap (0); OK (2);
  934. case RH_GET_STATUS | RH_ENDPOINT:
  935. *(__u16 *) data_buf = m16_swap (0); OK (2);
  936. case RH_GET_STATUS | RH_CLASS:
  937. *(__u32 *) data_buf = m32_swap (
  938. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  939. OK (4);
  940. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  941. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  942. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  943. switch (wValue) {
  944. case (RH_ENDPOINT_STALL): OK (0);
  945. }
  946. break;
  947. case RH_CLEAR_FEATURE | RH_CLASS:
  948. switch (wValue) {
  949. case RH_C_HUB_LOCAL_POWER:
  950. OK(0);
  951. case (RH_C_HUB_OVER_CURRENT):
  952. WR_RH_STAT(RH_HS_OCIC); OK (0);
  953. }
  954. break;
  955. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  956. switch (wValue) {
  957. case (RH_PORT_ENABLE):
  958. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  959. case (RH_PORT_SUSPEND):
  960. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  961. case (RH_PORT_POWER):
  962. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  963. case (RH_C_PORT_CONNECTION):
  964. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  965. case (RH_C_PORT_ENABLE):
  966. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  967. case (RH_C_PORT_SUSPEND):
  968. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  969. case (RH_C_PORT_OVER_CURRENT):
  970. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  971. case (RH_C_PORT_RESET):
  972. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  973. }
  974. break;
  975. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  976. switch (wValue) {
  977. case (RH_PORT_SUSPEND):
  978. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  979. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  980. if (RD_RH_PORTSTAT & RH_PS_CCS)
  981. WR_RH_PORTSTAT (RH_PS_PRS);
  982. OK (0);
  983. case (RH_PORT_POWER):
  984. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  985. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  986. if (RD_RH_PORTSTAT & RH_PS_CCS)
  987. WR_RH_PORTSTAT (RH_PS_PES );
  988. OK (0);
  989. }
  990. break;
  991. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  992. case RH_GET_DESCRIPTOR:
  993. switch ((wValue & 0xff00) >> 8) {
  994. case (0x01): /* device descriptor */
  995. len = min_t(unsigned int,
  996. leni,
  997. min_t(unsigned int,
  998. sizeof (root_hub_dev_des),
  999. wLength));
  1000. data_buf = root_hub_dev_des; OK(len);
  1001. case (0x02): /* configuration descriptor */
  1002. len = min_t(unsigned int,
  1003. leni,
  1004. min_t(unsigned int,
  1005. sizeof (root_hub_config_des),
  1006. wLength));
  1007. data_buf = root_hub_config_des; OK(len);
  1008. case (0x03): /* string descriptors */
  1009. if(wValue==0x0300) {
  1010. len = min_t(unsigned int,
  1011. leni,
  1012. min_t(unsigned int,
  1013. sizeof (root_hub_str_index0),
  1014. wLength));
  1015. data_buf = root_hub_str_index0;
  1016. OK(len);
  1017. }
  1018. if(wValue==0x0301) {
  1019. len = min_t(unsigned int,
  1020. leni,
  1021. min_t(unsigned int,
  1022. sizeof (root_hub_str_index1),
  1023. wLength));
  1024. data_buf = root_hub_str_index1;
  1025. OK(len);
  1026. }
  1027. default:
  1028. stat = USB_ST_STALLED;
  1029. }
  1030. break;
  1031. case RH_GET_DESCRIPTOR | RH_CLASS:
  1032. {
  1033. __u32 temp = roothub_a (&gohci);
  1034. data_buf [0] = 9; /* min length; */
  1035. data_buf [1] = 0x29;
  1036. data_buf [2] = temp & RH_A_NDP;
  1037. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1038. data_buf [2] = (data_buf [2] == 2) ? 1:0;
  1039. #endif
  1040. data_buf [3] = 0;
  1041. if (temp & RH_A_PSM) /* per-port power switching? */
  1042. data_buf [3] |= 0x1;
  1043. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1044. data_buf [3] |= 0x10;
  1045. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1046. data_buf [3] |= 0x8;
  1047. /* corresponds to data_buf[4-7] */
  1048. datab [1] = 0;
  1049. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1050. temp = roothub_b (&gohci);
  1051. data_buf [7] = temp & RH_B_DR;
  1052. if (data_buf [2] < 7) {
  1053. data_buf [8] = 0xff;
  1054. } else {
  1055. data_buf [0] += 2;
  1056. data_buf [8] = (temp & RH_B_DR) >> 8;
  1057. data_buf [10] = data_buf [9] = 0xff;
  1058. }
  1059. len = min_t(unsigned int, leni,
  1060. min_t(unsigned int, data_buf [0], wLength));
  1061. OK (len);
  1062. }
  1063. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1064. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1065. default:
  1066. dbg ("unsupported root hub command");
  1067. stat = USB_ST_STALLED;
  1068. }
  1069. #ifdef DEBUG
  1070. ohci_dump_roothub (&gohci, 1);
  1071. #else
  1072. wait_ms(1);
  1073. #endif
  1074. len = min_t(int, len, leni);
  1075. if (data != data_buf)
  1076. memcpy (data, data_buf, len);
  1077. dev->act_len = len;
  1078. dev->status = stat;
  1079. #ifdef DEBUG
  1080. if (transfer_len)
  1081. urb_priv.actual_length = transfer_len;
  1082. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1083. #else
  1084. wait_ms(1);
  1085. #endif
  1086. return stat;
  1087. }
  1088. /*-------------------------------------------------------------------------*/
  1089. /* common code for handling submit messages - used for all but root hub */
  1090. /* accesses. */
  1091. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1092. int transfer_len, struct devrequest *setup, int interval)
  1093. {
  1094. int stat = 0;
  1095. int maxsize = usb_maxpacket(dev, pipe);
  1096. int timeout;
  1097. /* device pulled? Shortcut the action. */
  1098. if (devgone == dev) {
  1099. dev->status = USB_ST_CRC_ERR;
  1100. return 0;
  1101. }
  1102. #ifdef DEBUG
  1103. urb_priv.actual_length = 0;
  1104. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1105. #else
  1106. wait_ms(1);
  1107. #endif
  1108. if (!maxsize) {
  1109. err("submit_common_message: pipesize for pipe %lx is zero",
  1110. pipe);
  1111. return -1;
  1112. }
  1113. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1114. err("sohci_submit_job failed");
  1115. return -1;
  1116. }
  1117. wait_ms(10);
  1118. /* ohci_dump_status(&gohci); */
  1119. /* allow more time for a BULK device to react - some are slow */
  1120. #define BULK_TO 5000 /* timeout in milliseconds */
  1121. if (usb_pipetype (pipe) == PIPE_BULK)
  1122. timeout = BULK_TO;
  1123. else
  1124. timeout = 100;
  1125. /* wait for it to complete */
  1126. for (;;) {
  1127. /* check whether the controller is done */
  1128. stat = hc_interrupt();
  1129. if (stat < 0) {
  1130. stat = USB_ST_CRC_ERR;
  1131. break;
  1132. }
  1133. #ifdef S3C24X0_merge
  1134. /* NOTE: since we are not interrupt driven in U-Boot and always
  1135. * handle only one URB at a time, we cannot assume the
  1136. * transaction finished on the first successful return from
  1137. * hc_interrupt().. unless the flag for current URB is set,
  1138. * meaning that all TD's to/from device got actually
  1139. * transferred and processed. If the current URB is not
  1140. * finished we need to re-iterate this loop so as
  1141. * hc_interrupt() gets called again as there needs to be some
  1142. * more TD's to process still */
  1143. if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
  1144. #else
  1145. if (stat >= 0 && stat != 0xff) {
  1146. #endif
  1147. /* 0xff is returned for an SF-interrupt */
  1148. break;
  1149. }
  1150. if (--timeout) {
  1151. wait_ms(1);
  1152. } else {
  1153. err("CTL:TIMEOUT ");
  1154. #ifdef S3C24X0_merge
  1155. dbg("submit_common_msg: TO status %x\n", stat);
  1156. urb_finished = 1;
  1157. #endif
  1158. stat = USB_ST_CRC_ERR;
  1159. break;
  1160. }
  1161. }
  1162. #ifndef S3C24X0_merge
  1163. /* we got an Root Hub Status Change interrupt */
  1164. if (got_rhsc) {
  1165. #ifdef DEBUG
  1166. ohci_dump_roothub (&gohci, 1);
  1167. #endif
  1168. got_rhsc = 0;
  1169. /* abuse timeout */
  1170. timeout = rh_check_port_status(&gohci);
  1171. if (timeout >= 0) {
  1172. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1173. /* the called routine adds 1 to the passed value */
  1174. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1175. #endif
  1176. /*
  1177. * XXX
  1178. * This is potentially dangerous because it assumes
  1179. * that only one device is ever plugged in!
  1180. */
  1181. devgone = dev;
  1182. }
  1183. }
  1184. #endif /* S3C24X0_merge */
  1185. dev->status = stat;
  1186. dev->act_len = transfer_len;
  1187. #ifdef DEBUG
  1188. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1189. #else
  1190. wait_ms(1);
  1191. #endif
  1192. /* free TDs in urb_priv */
  1193. urb_free_priv (&urb_priv);
  1194. return 0;
  1195. }
  1196. /* submit routines called from usb.c */
  1197. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1198. int transfer_len)
  1199. {
  1200. info("submit_bulk_msg");
  1201. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1202. }
  1203. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1204. int transfer_len, struct devrequest *setup)
  1205. {
  1206. int maxsize = usb_maxpacket(dev, pipe);
  1207. info("submit_control_msg");
  1208. #ifdef DEBUG
  1209. urb_priv.actual_length = 0;
  1210. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1211. #else
  1212. wait_ms(1);
  1213. #endif
  1214. if (!maxsize) {
  1215. err("submit_control_message: pipesize for pipe %lx is zero",
  1216. pipe);
  1217. return -1;
  1218. }
  1219. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1220. gohci.rh.dev = dev;
  1221. /* root hub - redirect */
  1222. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1223. setup);
  1224. }
  1225. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1226. }
  1227. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1228. int transfer_len, int interval)
  1229. {
  1230. info("submit_int_msg");
  1231. return -1;
  1232. }
  1233. /*-------------------------------------------------------------------------*
  1234. * HC functions
  1235. *-------------------------------------------------------------------------*/
  1236. /* reset the HC and BUS */
  1237. static int hc_reset (ohci_t *ohci)
  1238. {
  1239. int timeout = 30;
  1240. int smm_timeout = 50; /* 0,5 sec */
  1241. dbg("%s\n", __FUNCTION__);
  1242. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1243. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1244. info("USB HC TakeOver from SMM");
  1245. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1246. wait_ms (10);
  1247. if (--smm_timeout == 0) {
  1248. err("USB HC TakeOver failed!");
  1249. return -1;
  1250. }
  1251. }
  1252. }
  1253. /* Disable HC interrupts */
  1254. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1255. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1256. ohci->slot_name,
  1257. readl(&ohci->regs->control));
  1258. /* Reset USB (needed by some controllers) */
  1259. writel (0, &ohci->regs->control);
  1260. /* HC Reset requires max 10 us delay */
  1261. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1262. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1263. if (--timeout == 0) {
  1264. err("USB HC reset timed out!");
  1265. return -1;
  1266. }
  1267. udelay (1);
  1268. }
  1269. return 0;
  1270. }
  1271. /*-------------------------------------------------------------------------*/
  1272. /* Start an OHCI controller, set the BUS operational
  1273. * enable interrupts
  1274. * connect the virtual root hub */
  1275. static int hc_start (ohci_t * ohci)
  1276. {
  1277. __u32 mask;
  1278. unsigned int fminterval;
  1279. ohci->disabled = 1;
  1280. /* Tell the controller where the control and bulk lists are
  1281. * The lists are empty now. */
  1282. writel (0, &ohci->regs->ed_controlhead);
  1283. writel (0, &ohci->regs->ed_bulkhead);
  1284. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1285. fminterval = 0x2edf;
  1286. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1287. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1288. writel (fminterval, &ohci->regs->fminterval);
  1289. writel (0x628, &ohci->regs->lsthresh);
  1290. /* start controller operations */
  1291. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1292. ohci->disabled = 0;
  1293. writel (ohci->hc_control, &ohci->regs->control);
  1294. /* disable all interrupts */
  1295. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1296. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1297. OHCI_INTR_OC | OHCI_INTR_MIE);
  1298. writel (mask, &ohci->regs->intrdisable);
  1299. /* clear all interrupts */
  1300. mask &= ~OHCI_INTR_MIE;
  1301. writel (mask, &ohci->regs->intrstatus);
  1302. /* Choose the interrupts we care about now - but w/o MIE */
  1303. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1304. writel (mask, &ohci->regs->intrenable);
  1305. #ifdef OHCI_USE_NPS
  1306. /* required for AMD-756 and some Mac platforms */
  1307. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1308. &ohci->regs->roothub.a);
  1309. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1310. #endif /* OHCI_USE_NPS */
  1311. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1312. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1313. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1314. /* connect the virtual root hub */
  1315. ohci->rh.devnum = 0;
  1316. return 0;
  1317. }
  1318. /*-------------------------------------------------------------------------*/
  1319. /* an interrupt happens */
  1320. static int hc_interrupt (void)
  1321. {
  1322. ohci_t *ohci = &gohci;
  1323. struct ohci_regs *regs = ohci->regs;
  1324. int ints;
  1325. int stat = -1;
  1326. #ifdef S3C24X0_merge
  1327. if ((ohci->hcca->done_head != 0) &&
  1328. !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1329. ints = OHCI_INTR_WDH;
  1330. } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
  1331. ohci->disabled++;
  1332. err ("%s device removed!", ohci->slot_name);
  1333. return -1;
  1334. } else if ((ints &= readl (&regs->intrenable)) == 0) {
  1335. dbg("hc_interrupt: returning..\n");
  1336. return 0xff;
  1337. }
  1338. #else
  1339. if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1340. ints = OHCI_INTR_WDH;
  1341. } else {
  1342. ints = readl (&regs->intrstatus);
  1343. }
  1344. #endif
  1345. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1346. if (ints & OHCI_INTR_RHSC) {
  1347. got_rhsc = 1;
  1348. #ifdef S3C24X0_merge
  1349. stat = 0xff;
  1350. #endif
  1351. }
  1352. if (ints & OHCI_INTR_UE) {
  1353. ohci->disabled++;
  1354. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1355. ohci->slot_name);
  1356. /* e.g. due to PCI Master/Target Abort */
  1357. #ifdef DEBUG
  1358. ohci_dump (ohci, 1);
  1359. #else
  1360. wait_ms(1);
  1361. #endif
  1362. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1363. /* Make some non-interrupt context restart the controller. */
  1364. /* Count and limit the retries though; either hardware or */
  1365. /* software errors can go forever... */
  1366. hc_reset (ohci);
  1367. return -1;
  1368. }
  1369. if (ints & OHCI_INTR_WDH) {
  1370. wait_ms(1);
  1371. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1372. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1373. writel (OHCI_INTR_WDH, &regs->intrenable);
  1374. }
  1375. if (ints & OHCI_INTR_SO) {
  1376. dbg("USB Schedule overrun\n");
  1377. writel (OHCI_INTR_SO, &regs->intrenable);
  1378. stat = -1;
  1379. }
  1380. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1381. if (ints & OHCI_INTR_SF) {
  1382. unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
  1383. wait_ms(1);
  1384. writel (OHCI_INTR_SF, &regs->intrdisable);
  1385. if (ohci->ed_rm_list[frame] != NULL)
  1386. writel (OHCI_INTR_SF, &regs->intrenable);
  1387. stat = 0xff;
  1388. }
  1389. writel (ints, &regs->intrstatus);
  1390. return stat;
  1391. }
  1392. /*-------------------------------------------------------------------------*/
  1393. /*-------------------------------------------------------------------------*/
  1394. /* De-allocate all resources.. */
  1395. static void hc_release_ohci (ohci_t *ohci)
  1396. {
  1397. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1398. if (!ohci->disabled)
  1399. hc_reset (ohci);
  1400. }
  1401. /*-------------------------------------------------------------------------*/
  1402. /*
  1403. * low level initalisation routine, called from usb.c
  1404. */
  1405. static char ohci_inited = 0;
  1406. int usb_lowlevel_init(void)
  1407. {
  1408. #ifdef CFG_USB_OHCI_CPU_INIT
  1409. /* cpu dependant init */
  1410. if(usb_cpu_init())
  1411. return -1;
  1412. #endif
  1413. #ifdef CFG_USB_OHCI_BOARD_INIT
  1414. /* board dependant init */
  1415. if(usb_board_init())
  1416. return -1;
  1417. #endif
  1418. memset (&gohci, 0, sizeof (ohci_t));
  1419. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1420. /* align the storage */
  1421. if ((__u32)&ghcca[0] & 0xff) {
  1422. err("HCCA not aligned!!");
  1423. return -1;
  1424. }
  1425. phcca = &ghcca[0];
  1426. info("aligned ghcca %p", phcca);
  1427. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1428. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1429. err("EDs not aligned!!");
  1430. return -1;
  1431. }
  1432. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1433. if ((__u32)gtd & 0x7) {
  1434. err("TDs not aligned!!");
  1435. return -1;
  1436. }
  1437. ptd = gtd;
  1438. gohci.hcca = phcca;
  1439. memset (phcca, 0, sizeof (struct ohci_hcca));
  1440. gohci.disabled = 1;
  1441. gohci.sleeping = 0;
  1442. gohci.irq = -1;
  1443. gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
  1444. gohci.flags = 0;
  1445. gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
  1446. if (hc_reset (&gohci) < 0) {
  1447. hc_release_ohci (&gohci);
  1448. err ("can't reset usb-%s", gohci.slot_name);
  1449. #ifdef CFG_USB_OHCI_BOARD_INIT
  1450. /* board dependant cleanup */
  1451. usb_board_init_fail();
  1452. #endif
  1453. #ifdef CFG_USB_OHCI_CPU_INIT
  1454. /* cpu dependant cleanup */
  1455. usb_cpu_init_fail();
  1456. #endif
  1457. return -1;
  1458. }
  1459. /* FIXME this is a second HC reset; why?? */
  1460. /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
  1461. wait_ms(10); */
  1462. if (hc_start (&gohci) < 0) {
  1463. err ("can't start usb-%s", gohci.slot_name);
  1464. hc_release_ohci (&gohci);
  1465. /* Initialization failed */
  1466. #ifdef CFG_USB_OHCI_BOARD_INIT
  1467. /* board dependant cleanup */
  1468. usb_board_stop();
  1469. #endif
  1470. #ifdef CFG_USB_OHCI_CPU_INIT
  1471. /* cpu dependant cleanup */
  1472. usb_cpu_stop();
  1473. #endif
  1474. return -1;
  1475. }
  1476. #ifdef DEBUG
  1477. ohci_dump (&gohci, 1);
  1478. #else
  1479. wait_ms(1);
  1480. # ifdef S3C24X0_merge
  1481. urb_finished = 1;
  1482. # endif
  1483. #endif
  1484. ohci_inited = 1;
  1485. return 0;
  1486. }
  1487. int usb_lowlevel_stop(void)
  1488. {
  1489. /* this gets called really early - before the controller has */
  1490. /* even been initialized! */
  1491. if (!ohci_inited)
  1492. return 0;
  1493. /* TODO release any interrupts, etc. */
  1494. /* call hc_release_ohci() here ? */
  1495. hc_reset (&gohci);
  1496. #ifdef CFG_USB_OHCI_BOARD_INIT
  1497. /* board dependant cleanup */
  1498. if(usb_board_stop())
  1499. return -1;
  1500. #endif
  1501. #ifdef CFG_USB_OHCI_CPU_INIT
  1502. /* cpu dependant cleanup */
  1503. if(usb_cpu_stop())
  1504. return -1;
  1505. #endif
  1506. return 0;
  1507. }
  1508. #endif /* CONFIG_USB_OHCI */