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phyus
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uboot-vybrid_public
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uboot-vybrid_pu...
/
include
/
asm-blackfin
/
mach-bf537
/
BF537_cdef.h

BF537_cdef.h 20 KB
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  1. /* DO NOT EDIT THIS FILE
    2. 

  2.  * Automatically generated by generate-cdef-headers.xsl
    3. 

  3.  * DO NOT EDIT THIS FILE
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef __BFIN_CDEF_ADSP_BF537_proc__
    7. 

  7. #define __BFIN_CDEF_ADSP_BF537_proc__
    8. 

  8. 

  9. #include "../mach-common/ADSP-EDN-core_cdef.h"
    10. 

  10. 

  11. #include "ADSP-EDN-BF534-extended_cdef.h"
    12. 

  12. 

  13. #define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
    14. 

  14. #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
    15. 

  15. #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
    16. 

  16. #define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
    17. 

  17. #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
    18. 

  18. #define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
    19. 

  19. #define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
    20. 

  20. #define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
    21. 

  21. #define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
    22. 

  22. #define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
    23. 

  23. #define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
    24. 

  24. #define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
    25. 

  25. #define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
    26. 

  26. #define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
    27. 

  27. #define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
    28. 

  28. #define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
    29. 

  29. #define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
    30. 

  30. #define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
    31. 

  31. #define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
    32. 

  32. #define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
    33. 

  33. #define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
    34. 

  34. #define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
    35. 

  35. #define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
    36. 

  36. #define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
    37. 

  37. #define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
    38. 

  38. #define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
    39. 

  39. #define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
    40. 

  40. #define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
    41. 

  41. #define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
    42. 

  42. #define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
    43. 

  43. #define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
    44. 

  44. #define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
    45. 

  45. #define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
    46. 

  46. #define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
    47. 

  47. #define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
    48. 

  48. #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
    49. 

  49. #define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
    50. 

  50. #define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
    51. 

  51. #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
    52. 

  52. #define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
    53. 

  53. #define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
    54. 

  54. #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
    55. 

  55. #define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
    56. 

  56. #define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
    57. 

  57. #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
    58. 

  58. #define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
    59. 

  59. #define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
    60. 

  60. #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
    61. 

  61. #define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
    62. 

  62. #define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
    63. 

  63. #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
    64. 

  64. #define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
    65. 

  65. #define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
    66. 

  66. #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
    67. 

  67. #define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
    68. 

  68. #define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
    69. 

  69. #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
    70. 

  70. #define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
    71. 

  71. #define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
    72. 

  72. #define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
    73. 

  73. #define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
    74. 

  74. #define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
    75. 

  75. #define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
    76. 

  76. #define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
    77. 

  77. #define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
    78. 

  78. #define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
    79. 

  79. #define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
    80. 

  80. #define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
    81. 

  81. #define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
    82. 

  82. #define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
    83. 

  83. #define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
    84. 

  84. #define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
    85. 

  85. #define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
    86. 

  86. #define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
    87. 

  87. #define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
    88. 

  88. #define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
    89. 

  89. #define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
    90. 

  90. #define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
    91. 

  91. #define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
    92. 

  92. #define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
    93. 

  93. #define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
    94. 

  94. #define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
    95. 

  95. #define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
    96. 

  96. #define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
    97. 

  97. #define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
    98. 

  98. #define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
    99. 

  99. #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
    100. 

  100. #define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
    101. 

  101. #define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
    102. 

  102. #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
    103. 

  103. #define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
    104. 

  104. #define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
    105. 

  105. #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
    106. 

  106. #define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
    107. 

  107. #define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
    108. 

  108. #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
    109. 

  109. #define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
    110. 

  110. #define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
    111. 

  111. #define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
    112. 

  112. #define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
    113. 

  113. #define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
    114. 

  114. #define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
    115. 

  115. #define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
    116. 

  116. #define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
    117. 

  117. #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
    118. 

  118. #define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
    119. 

  119. #define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
    120. 

  120. #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
    121. 

  121. #define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
    122. 

  122. #define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
    123. 

  123. #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
    124. 

  124. #define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
    125. 

  125. #define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
    126. 

  126. #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
    127. 

  127. #define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
    128. 

  128. #define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
    129. 

  129. #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
    130. 

  130. #define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
    131. 

  131. #define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
    132. 

  132. #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
    133. 

  133. #define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
    134. 

  134. #define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
    135. 

  135. #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
    136. 

  136. #define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
    137. 

  137. #define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
    138. 

  138. #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
    139. 

  139. #define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
    140. 

  140. #define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
    141. 

  141. #define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
    142. 

  142. #define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
    143. 

  143. #define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
    144. 

  144. #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
    145. 

  145. #define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
    146. 

  146. #define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
    147. 

  147. #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
    148. 

  148. #define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
    149. 

  149. #define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
    150. 

  150. #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
    151. 

  151. #define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
    152. 

  152. #define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
    153. 

  153. #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
    154. 

  154. #define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
    155. 

  155. #define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
    156. 

  156. #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
    157. 

  157. #define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
    158. 

  158. #define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
    159. 

  159. #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
    160. 

  160. #define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
    161. 

  161. #define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
    162. 

  162. #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
    163. 

  163. #define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
    164. 

  164. #define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
    165. 

  165. #define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
    166. 

  166. #define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
    167. 

  167. #define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
    168. 

  168. #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
    169. 

  169. #define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
    170. 

  170. #define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
    171. 

  171. #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
    172. 

  172. #define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
    173. 

  173. #define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
    174. 

  174. #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
    175. 

  175. #define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
    176. 

  176. #define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
    177. 

  177. #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
    178. 

  178. #define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
    179. 

  179. #define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
    180. 

  180. #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
    181. 

  181. #define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
    182. 

  182. #define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
    183. 

  183. #define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
    184. 

  184. #define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
    185. 

  185. #define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
    186. 

  186. #define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
    187. 

  187. #define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
    188. 

  188. #define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
    189. 

  189. #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
    190. 

  190. #define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
    191. 

  191. #define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
    192. 

  192. #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
    193. 

  193. #define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
    194. 

  194. #define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
    195. 

  195. #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
    196. 

  196. #define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
    197. 

  197. #define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
    198. 

  198. #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
    199. 

  199. #define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
    200. 

  200. #define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
    201. 

  201. #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
    202. 

  202. #define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
    203. 

  203. #define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
    204. 

  204. #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
    205. 

  205. #define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
    206. 

  206. #define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
    207. 

  207. #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
    208. 

  208. #define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
    209. 

  209. #define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
    210. 

  210. #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
    211. 

  211. #define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
    212. 

  212. #define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
    213. 

  213. #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
    214. 

  214. #define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
    215. 

  215. #define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
    216. 

  216. #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
    217. 

  217. #define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
    218. 

  218. #define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
    219. 

  219. #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
    220. 

  220. #define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
    221. 

  221. #define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
    222. 

  222. #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
    223. 

  223. #define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
    224. 

  224. #define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
    225. 

  225. #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
    226. 

  226. #define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
    227. 

  227. #define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
    228. 

  228. #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
    229. 

  229. #define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
    230. 

  230. #define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
    231. 

  231. #define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
    232. 

  232. #define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
    233. 

  233. #define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
    234. 

  234. #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
    235. 

  235. #define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
    236. 

  236. #define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
    237. 

  237. #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
    238. 

  238. #define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
    239. 

  239. #define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
    240. 

  240. #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
    241. 

  241. #define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
    242. 

  242. #define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
    243. 

  243. #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
    244. 

  244. #define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
    245. 

  245. #define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
    246. 

  246. #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
    247. 

  247. #define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
    248. 

  248. #define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
    249. 

  249. #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
    250. 

  250. 

  251. #endif /* __BFIN_CDEF_ADSP_BF537_proc__ */
    252.