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AT91RM9200.h

AT91RM9200.h 22 KB
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  1. /*  ---------------------------------------------------------------------------- */
    2. 

  2. /*           ATMEL Microcontroller Software Support  -  ROUSSET  - */
    3. 

  3. /*  ---------------------------------------------------------------------------- */
    4. 

  4. /*   The software is delivered "AS IS" without warranty or condition of any */
    5. 

  5. /*   kind, either express, implied or statutory. This includes without */
    6. 

  6. /*   limitation any warranty or condition with respect to merchantability or */
    7. 

  7. /*   fitness for any particular purpose, or against the infringements of */
    8. 

  8. /*   intellectual property rights of others. */
    9. 

  9. /*  ---------------------------------------------------------------------------- */
    10. 

  10. /*  File Name           : AT91RM9200.h */
    11. 

  11. /*  Object              : AT91RM9200 definitions */
    12. 

  12. /*  Generated           : AT91 SW Application Group  10/29/2002 (16:10:51) */
    13. 

  13. #ifndef AT91RM9200_H
    14. 

  14. #define AT91RM9200_H
    15. 

  15. 

  16. typedef volatile unsigned int AT91_REG;/*  Hardware register definition */
    17. 

  17. 

  18. /*  ***************************************************************************** */
    19. 

  19. /*               SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
    20. 

  20. /*  ***************************************************************************** */
    21. 

  21. typedef struct _AT91S_TC {
    22. 

  22. 	AT91_REG	 TC_CCR; 	/*  Channel Control Register */
    23. 

  23. 	AT91_REG	 TC_CMR; 	/*  Channel Mode Register */
    24. 

  24. 	AT91_REG	 Reserved0[2]; 	/*   */
    25. 

  25. 	AT91_REG	 TC_CV; 	/*  Counter Value */
    26. 

  26. 	AT91_REG	 TC_RA; 	/*  Register A */
    27. 

  27. 	AT91_REG	 TC_RB; 	/*  Register B */
    28. 

  28. 	AT91_REG	 TC_RC; 	/*  Register C */
    29. 

  29. 	AT91_REG	 TC_SR; 	/*  Status Register */
    30. 

  30. 	AT91_REG	 TC_IER; 	/*  Interrupt Enable Register */
    31. 

  31. 	AT91_REG	 TC_IDR; 	/*  Interrupt Disable Register */
    32. 

  32. 	AT91_REG	 TC_IMR; 	/*  Interrupt Mask Register */
    33. 

  33. } AT91S_TC, *AT91PS_TC;
    34. 

  34. 

  35. /*  ***************************************************************************** */
    36. 

  36. /*               SOFTWARE API DEFINITION  FOR Usart */
    37. 

  37. /*  ***************************************************************************** */
    38. 

  38. typedef struct _AT91S_USART {
    39. 

  39. 	AT91_REG	 US_CR; 	/*  Control Register */
    40. 

  40. 	AT91_REG	 US_MR; 	/*  Mode Register */
    41. 

  41. 	AT91_REG	 US_IER; 	/*  Interrupt Enable Register */
    42. 

  42. 	AT91_REG	 US_IDR; 	/*  Interrupt Disable Register */
    43. 

  43. 	AT91_REG	 US_IMR; 	/*  Interrupt Mask Register */
    44. 

  44. 	AT91_REG	 US_CSR; 	/*  Channel Status Register */
    45. 

  45. 	AT91_REG	 US_RHR; 	/*  Receiver Holding Register */
    46. 

  46. 	AT91_REG	 US_THR; 	/*  Transmitter Holding Register */
    47. 

  47. 	AT91_REG	 US_BRGR; 	/*  Baud Rate Generator Register */
    48. 

  48. 	AT91_REG	 US_RTOR; 	/*  Receiver Time-out Register */
    49. 

  49. 	AT91_REG	 US_TTGR; 	/*  Transmitter Time-guard Register */
    50. 

  50. 	AT91_REG	 Reserved0[5]; 	/*   */
    51. 

  51. 	AT91_REG	 US_FIDI; 	/*  FI_DI_Ratio Register */
    52. 

  52. 	AT91_REG	 US_NER; 	/*  Nb Errors Register */
    53. 

  53. 	AT91_REG	 US_XXR; 	/*  XON_XOFF Register */
    54. 

  54. 	AT91_REG	 US_IF; 	/*  IRDA_FILTER Register */
    55. 

  55. 	AT91_REG	 Reserved1[44]; 	/*   */
    56. 

  56. 	AT91_REG	 US_RPR; 	/*  Receive Pointer Register */
    57. 

  57. 	AT91_REG	 US_RCR; 	/*  Receive Counter Register */
    58. 

  58. 	AT91_REG	 US_TPR; 	/*  Transmit Pointer Register */
    59. 

  59. 	AT91_REG	 US_TCR; 	/*  Transmit Counter Register */
    60. 

  60. 	AT91_REG	 US_RNPR; 	/*  Receive Next Pointer Register */
    61. 

  61. 	AT91_REG	 US_RNCR; 	/*  Receive Next Counter Register */
    62. 

  62. 	AT91_REG	 US_TNPR; 	/*  Transmit Next Pointer Register */
    63. 

  63. 	AT91_REG	 US_TNCR; 	/*  Transmit Next Counter Register */
    64. 

  64. 	AT91_REG	 US_PTCR; 	/*  PDC Transfer Control Register */
    65. 

  65. 	AT91_REG	 US_PTSR; 	/*  PDC Transfer Status Register */
    66. 

  66. } AT91S_USART, *AT91PS_USART;
    67. 

  67. 

  68. /*  ***************************************************************************** */
    69. 

  69. /*               SOFTWARE API DEFINITION  FOR Parallel Input Output Controler */
    70. 

  70. /*  ***************************************************************************** */
    71. 

  71. typedef struct _AT91S_PIO {
    72. 

  72. 	AT91_REG	 PIO_PER; 	/*  PIO Enable Register */
    73. 

  73. 	AT91_REG	 PIO_PDR; 	/*  PIO Disable Register */
    74. 

  74. 	AT91_REG	 PIO_PSR; 	/*  PIO Status Register */
    75. 

  75. 	AT91_REG	 Reserved0[1]; 	/*   */
    76. 

  76. 	AT91_REG	 PIO_OER; 	/*  Output Enable Register */
    77. 

  77. 	AT91_REG	 PIO_ODR; 	/*  Output Disable Registerr */
    78. 

  78. 	AT91_REG	 PIO_OSR; 	/*  Output Status Register */
    79. 

  79. 	AT91_REG	 Reserved1[1]; 	/*   */
    80. 

  80. 	AT91_REG	 PIO_IFER; 	/*  Input Filter Enable Register */
    81. 

  81. 	AT91_REG	 PIO_IFDR; 	/*  Input Filter Disable Register */
    82. 

  82. 	AT91_REG	 PIO_IFSR; 	/*  Input Filter Status Register */
    83. 

  83. 	AT91_REG	 Reserved2[1]; 	/*   */
    84. 

  84. 	AT91_REG	 PIO_SODR; 	/*  Set Output Data Register */
    85. 

  85. 	AT91_REG	 PIO_CODR; 	/*  Clear Output Data Register */
    86. 

  86. 	AT91_REG	 PIO_ODSR; 	/*  Output Data Status Register */
    87. 

  87. 	AT91_REG	 PIO_PDSR; 	/*  Pin Data Status Register */
    88. 

  88. 	AT91_REG	 PIO_IER; 	/*  Interrupt Enable Register */
    89. 

  89. 	AT91_REG	 PIO_IDR; 	/*  Interrupt Disable Register */
    90. 

  90. 	AT91_REG	 PIO_IMR; 	/*  Interrupt Mask Register */
    91. 

  91. 	AT91_REG	 PIO_ISR; 	/*  Interrupt Status Register */
    92. 

  92. 	AT91_REG	 PIO_MDER; 	/*  Multi-driver Enable Register */
    93. 

  93. 	AT91_REG	 PIO_MDDR; 	/*  Multi-driver Disable Register */
    94. 

  94. 	AT91_REG	 PIO_MDSR; 	/*  Multi-driver Status Register */
    95. 

  95. 	AT91_REG	 Reserved3[1]; 	/*   */
    96. 

  96. 	AT91_REG	 PIO_PPUDR; 	/*  Pull-up Disable Register */
    97. 

  97. 	AT91_REG	 PIO_PPUER; 	/*  Pull-up Enable Register */
    98. 

  98. 	AT91_REG	 PIO_PPUSR; 	/*  Pad Pull-up Status Register */
    99. 

  99. 	AT91_REG	 Reserved4[1]; 	/*   */
    100. 

  100. 	AT91_REG	 PIO_ASR; 	/*  Select A Register */
    101. 

  101. 	AT91_REG	 PIO_BSR; 	/*  Select B Register */
    102. 

  102. 	AT91_REG	 PIO_ABSR; 	/*  AB Select Status Register */
    103. 

  103. 	AT91_REG	 Reserved5[9]; 	/*   */
    104. 

  104. 	AT91_REG	 PIO_OWER; 	/*  Output Write Enable Register */
    105. 

  105. 	AT91_REG	 PIO_OWDR; 	/*  Output Write Disable Register */
    106. 

  106. 	AT91_REG	 PIO_OWSR; 	/*  Output Write Status Register */
    107. 

  107. } AT91S_PIO, *AT91PS_PIO;
    108. 

  108. 

  109. 

  110. /*  ***************************************************************************** */
    111. 

  111. /*               SOFTWARE API DEFINITION  FOR Debug Unit */
    112. 

  112. /*  ***************************************************************************** */
    113. 

  113. typedef struct _AT91S_DBGU {
    114. 

  114. 	AT91_REG	 DBGU_CR; 	/*  Control Register */
    115. 

  115. 	AT91_REG	 DBGU_MR; 	/*  Mode Register */
    116. 

  116. 	AT91_REG	 DBGU_IER; 	/*  Interrupt Enable Register */
    117. 

  117. 	AT91_REG	 DBGU_IDR; 	/*  Interrupt Disable Register */
    118. 

  118. 	AT91_REG	 DBGU_IMR; 	/*  Interrupt Mask Register */
    119. 

  119. 	AT91_REG	 DBGU_CSR; 	/*  Channel Status Register */
    120. 

  120. 	AT91_REG	 DBGU_RHR; 	/*  Receiver Holding Register */
    121. 

  121. 	AT91_REG	 DBGU_THR; 	/*  Transmitter Holding Register */
    122. 

  122. 	AT91_REG	 DBGU_BRGR; 	/*  Baud Rate Generator Register */
    123. 

  123. 	AT91_REG	 Reserved0[7]; 	/*   */
    124. 

  124. 	AT91_REG	 DBGU_C1R; 	/*  Chip ID1 Register */
    125. 

  125. 	AT91_REG	 DBGU_C2R; 	/*  Chip ID2 Register */
    126. 

  126. 	AT91_REG	 DBGU_FNTR; 	/*  Force NTRST Register */
    127. 

  127. 	AT91_REG	 Reserved1[45]; 	/*   */
    128. 

  128. 	AT91_REG	 DBGU_RPR; 	/*  Receive Pointer Register */
    129. 

  129. 	AT91_REG	 DBGU_RCR; 	/*  Receive Counter Register */
    130. 

  130. 	AT91_REG	 DBGU_TPR; 	/*  Transmit Pointer Register */
    131. 

  131. 	AT91_REG	 DBGU_TCR; 	/*  Transmit Counter Register */
    132. 

  132. 	AT91_REG	 DBGU_RNPR; 	/*  Receive Next Pointer Register */
    133. 

  133. 	AT91_REG	 DBGU_RNCR; 	/*  Receive Next Counter Register */
    134. 

  134. 	AT91_REG	 DBGU_TNPR; 	/*  Transmit Next Pointer Register */
    135. 

  135. 	AT91_REG	 DBGU_TNCR; 	/*  Transmit Next Counter Register */
    136. 

  136. 	AT91_REG	 DBGU_PTCR; 	/*  PDC Transfer Control Register */
    137. 

  137. 	AT91_REG	 DBGU_PTSR; 	/*  PDC Transfer Status Register */
    138. 

  138. } AT91S_DBGU, *AT91PS_DBGU;
    139. 

  139. 

  140. 

  141. /*  ***************************************************************************** */
    142. 

  142. /*               SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface */
    143. 

  143. /*  ***************************************************************************** */
    144. 

  144. typedef struct _AT91S_SMC2 {
    145. 

  145. 	AT91_REG	 SMC2_CSR[8]; 	/*  SMC2 Chip Select Register */
    146. 

  146. } AT91S_SMC2, *AT91PS_SMC2;
    147. 

  147. 

  148. /*  ***************************************************************************** */
    149. 

  149. /*               SOFTWARE API DEFINITION  FOR Ethernet MAC */
    150. 

  150. /*  ***************************************************************************** */
    151. 

  151. typedef struct _AT91S_EMAC {
    152. 

  152. 	AT91_REG	 EMAC_CTL; 	/*  Network Control Register */
    153. 

  153. 	AT91_REG	 EMAC_CFG; 	/*  Network Configuration Register */
    154. 

  154. 	AT91_REG	 EMAC_SR; 	/*  Network Status Register */
    155. 

  155. 	AT91_REG	 EMAC_TAR; 	/*  Transmit Address Register */
    156. 

  156. 	AT91_REG	 EMAC_TCR; 	/*  Transmit Control Register */
    157. 

  157. 	AT91_REG	 EMAC_TSR; 	/*  Transmit Status Register */
    158. 

  158. 	AT91_REG	 EMAC_RBQP; 	/*  Receive Buffer Queue Pointer */
    159. 

  159. 	AT91_REG	 Reserved0[1]; 	/*   */
    160. 

  160. 	AT91_REG	 EMAC_RSR; 	/*  Receive Status Register */
    161. 

  161. 	AT91_REG	 EMAC_ISR; 	/*  Interrupt Status Register */
    162. 

  162. 	AT91_REG	 EMAC_IER; 	/*  Interrupt Enable Register */
    163. 

  163. 	AT91_REG	 EMAC_IDR; 	/*  Interrupt Disable Register */
    164. 

  164. 	AT91_REG	 EMAC_IMR; 	/*  Interrupt Mask Register */
    165. 

  165. 	AT91_REG	 EMAC_MAN; 	/*  PHY Maintenance Register */
    166. 

  166. 	AT91_REG	 Reserved1[2]; 	/*   */
    167. 

  167. 	AT91_REG	 EMAC_FRA; 	/*  Frames Transmitted OK Register */
    168. 

  168. 	AT91_REG	 EMAC_SCOL; 	/*  Single Collision Frame Register */
    169. 

  169. 	AT91_REG	 EMAC_MCOL; 	/*  Multiple Collision Frame Register */
    170. 

  170. 	AT91_REG	 EMAC_OK; 	/*  Frames Received OK Register */
    171. 

  171. 	AT91_REG	 EMAC_SEQE; 	/*  Frame Check Sequence Error Register */
    172. 

  172. 	AT91_REG	 EMAC_ALE; 	/*  Alignment Error Register */
    173. 

  173. 	AT91_REG	 EMAC_DTE; 	/*  Deferred Transmission Frame Register */
    174. 

  174. 	AT91_REG	 EMAC_LCOL; 	/*  Late Collision Register */
    175. 

  175. 	AT91_REG	 EMAC_ECOL; 	/*  Excessive Collision Register */
    176. 

  176. 	AT91_REG	 EMAC_CSE; 	/*  Carrier Sense Error Register */
    177. 

  177. 	AT91_REG	 EMAC_TUE; 	/*  Transmit Underrun Error Register */
    178. 

  178. 	AT91_REG	 EMAC_CDE; 	/*  Code Error Register */
    179. 

  179. 	AT91_REG	 EMAC_ELR; 	/*  Excessive Length Error Register */
    180. 

  180. 	AT91_REG	 EMAC_RJB; 	/*  Receive Jabber Register */
    181. 

  181. 	AT91_REG	 EMAC_USF; 	/*  Undersize Frame Register */
    182. 

  182. 	AT91_REG	 EMAC_SQEE; 	/*  SQE Test Error Register */
    183. 

  183. 	AT91_REG	 EMAC_DRFC; 	/*  Discarded RX Frame Register */
    184. 

  184. 	AT91_REG	 Reserved2[3]; 	/*   */
    185. 

  185. 	AT91_REG	 EMAC_HSH; 	/*  Hash Address High[63:32] */
    186. 

  186. 	AT91_REG	 EMAC_HSL; 	/*  Hash Address Low[31:0] */
    187. 

  187. 	AT91_REG	 EMAC_SA1L; 	/*  Specific Address 1 Low, First 4 bytes */
    188. 

  188. 	AT91_REG	 EMAC_SA1H; 	/*  Specific Address 1 High, Last 2 bytes */
    189. 

  189. 	AT91_REG	 EMAC_SA2L; 	/*  Specific Address 2 Low, First 4 bytes */
    190. 

  190. 	AT91_REG	 EMAC_SA2H; 	/*  Specific Address 2 High, Last 2 bytes */
    191. 

  191. 	AT91_REG	 EMAC_SA3L; 	/*  Specific Address 3 Low, First 4 bytes */
    192. 

  192. 	AT91_REG	 EMAC_SA3H; 	/*  Specific Address 3 High, Last 2 bytes */
    193. 

  193. 	AT91_REG	 EMAC_SA4L; 	/*  Specific Address 4 Low, First 4 bytes */
    194. 

  194. 	AT91_REG	 EMAC_SA4H; 	/*  Specific Address 4 High, Last 2 bytesr */
    195. 

  195. } AT91S_EMAC, *AT91PS_EMAC;
    196. 

  196. 

  197. /*  -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
    198. 

  198. #define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) /*  (DBGU) RXRDY Interrupt */
    199. 

  199. #define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) /*  (DBGU) TXRDY Interrupt */
    200. 

  200. #define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) /*  (DBGU) End of Receive Transfer Interrupt */
    201. 

  201. #define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) /*  (DBGU) End of Transmit Interrupt */
    202. 

  202. #define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) /*  (DBGU) Overrun Interrupt */
    203. 

  203. #define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) /*  (DBGU) Framing Error Interrupt */
    204. 

  204. #define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) /*  (DBGU) Parity Error Interrupt */
    205. 

  205. #define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) /*  (DBGU) TXEMPTY Interrupt */
    206. 

  206. #define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) /*  (DBGU) TXBUFE Interrupt */
    207. 

  207. #define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) /*  (DBGU) RXBUFF Interrupt */
    208. 

  208. #define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) /*  (DBGU) COMM_TX Interrupt */
    209. 

  209. #define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) /*  (DBGU) COMM_RX Interrupt */
    210. 

  210. 

  211. /*  -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  */
    212. 

  212. #define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) /*  (DBGU) Reset Receiver */
    213. 

  213. #define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) /*  (DBGU) Reset Transmitter */
    214. 

  214. #define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) /*  (DBGU) Receiver Enable */
    215. 

  215. #define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) /*  (DBGU) Receiver Disable */
    216. 

  216. #define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) /*  (DBGU) Transmitter Enable */
    217. 

  217. #define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) /*  (DBGU) Transmitter Disable */
    218. 

  218. 

  219. #define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) /*  (USART) Clock */
    220. 

  220. #define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) /*  (USART) Character Length: 8 bits */
    221. 

  221. #define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) /*  (DBGU) No Parity */
    222. 

  222. #define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) /*  (USART) 1 stop bit */
    223. 

  223. 

  224. #define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) /*  (PMC) Peripheral Clock Enable Register */
    225. 

  225. #define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) /*  (PIOA) PIO Disable Register */
    226. 

  226. #define AT91C_PIO_PA30       ((unsigned int) 1 << 30) /*  Pin Controlled by PA30 */
    227. 

  227. #define AT91C_PIO_PC0        ((unsigned int) 1 <<  0) /*  Pin Controlled by PC0 */
    228. 

  228. #define AT91C_PC0_BFCK     ((unsigned int) AT91C_PIO_PC0) /*   Burst Flash Clock */
    229. 

  229. #define AT91C_PA30_DRXD     ((unsigned int) AT91C_PIO_PA30) /*   DBGU Debug Receive Data */
    230. 

  230. #define AT91C_PIO_PA31       ((unsigned int) 1 << 31) /*  Pin Controlled by PA31 */
    231. 

  231. #define AT91C_PA31_DTXD     ((unsigned int) AT91C_PIO_PA31) /*   DBGU Debug Transmit Data */
    232. 

  232. 

  233. #define AT91C_ID_SYS    ((unsigned int)  1) /*  System Peripheral */
    234. 

  234. #define AT91C_ID_TC0    ((unsigned int) 17) /*  Timer Counter 0 */
    235. 

  235. #define AT91C_ID_EMAC   ((unsigned int) 24) /*  Ethernet MAC */
    236. 

  236. 

  237. #define AT91C_PIO_PC1        ((unsigned int) 1 <<  1) /*  Pin Controlled by PC1 */
    238. 

  238. #define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /*   Burst Flash Ready */
    239. 

  239. #define AT91C_PIO_PC3        ((unsigned int) 1 <<  3) /*  Pin Controlled by PC3 */
    240. 

  240. #define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /*   Burst Flash Address Advance / SmartMedia Write Enable */
    241. 

  241. #define AT91C_PIO_PC2        ((unsigned int) 1 <<  2) /*  Pin Controlled by PC2 */
    242. 

  242. #define AT91C_PC2_BFAVD    ((unsigned int) AT91C_PIO_PC2) /*   Burst Flash Address Valid */
    243. 

  243. #define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) /*  Pin Controlled by PB1 */
    244. 

  244. 

  245. #define AT91C_TC_TIMER_DIV1_CLOCK      ((unsigned int) 0x0 <<  0) /*  (TC) MCK/2 */
    246. 

  246. #define AT91C_TC_TIMER_DIV2_CLOCK      ((unsigned int) 0x1 <<  0) /*  (TC) MCK/8 */
    247. 

  247. #define AT91C_TC_TIMER_DIV3_CLOCK      ((unsigned int) 0x2 <<  0) /*  (TC) MCK/32 */
    248. 

  248. #define AT91C_TC_TIMER_DIV4_CLOCK      ((unsigned int) 0x3 <<  0) /*  (TC) MCK/128 */
    249. 

  249. #define AT91C_TC_SLOW_CLOCK            ((unsigned int) 0x4 <<  0) /*  (TC) SLOW CLK */
    250. 

  250. #define AT91C_TC_XC0_CLOCK             ((unsigned int) 0x5 <<  0) /*  (TC) XC0 */
    251. 

  251. #define AT91C_TC_XC1_CLOCK             ((unsigned int) 0x6 <<  0) /*  (TC) XC1 */
    252. 

  252. #define AT91C_TC_XC2_CLOCK             ((unsigned int) 0x7 <<  0) /*  (TC) XC2 */
    253. 

  253. #define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) /*  (TCB) None signal connected to XC0 */
    254. 

  254. #define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) /*  (TCB) None signal connected to XC1 */
    255. 

  255. #define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) /*  (TCB) None signal connected to XC2 */
    256. 

  256. #define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) /*  (TC) Counter Clock Disable Command */
    257. 

  257. #define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) /*  (TC) Software Trigger Command */
    258. 

  258. #define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) /*  (TC) Counter Clock Enable Command */
    259. 

  259. 

  260. #define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) /*  (EMAC)  */
    261. 

  261. #define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) /*  (EMAC)  */
    262. 

  262. #define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) /*  (EMAC)  */
    263. 

  263. #define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) /*  (EMAC) Receive enable.  */
    264. 

  264. #define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) /*  (EMAC) Transmit enable.  */
    265. 

  265. #define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) /*  (EMAC)  */
    266. 

  266. #define AT91C_EMAC_RMII       ((unsigned int) 0x1 << 13) /*  (EMAC)  */
    267. 

  267. #define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) /*  (EMAC) No broadcast.  */
    268. 

  268. #define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) /*  (EMAC) Copy all frames.  */
    269. 

  269. #define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) /*  (EMAC)  */
    270. 

  270. #define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) /*  (EMAC)  */
    271. 

  271. #define AT91C_EMAC_RSR_OVR    ((unsigned int) 0x1 <<  2) /*  (EMAC)  */
    272. 

  272. #define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) /*  (EMAC) Clear statistics registers.  */
    273. 

  273. #define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) /*  (EMAC) Speed.  */
    274. 

  274. #define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) /*  (EMAC) Full duplex.  */
    275. 

  275. #define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  0) /*  (EMAC)  */
    276. 

  276. #define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) /*  (EMAC) Management port enable.  */
    277. 

  277. #define AT91C_PIO_PA16       ((unsigned int) 1 << 16) /*  Pin Controlled by PA16 */
    278. 

  278. #define AT91C_PA16_EMDIO    ((unsigned int) AT91C_PIO_PA16) /*   Ethernet MAC Management Data Input/Output */
    279. 

  279. #define AT91C_PIO_PA15       ((unsigned int) 1 << 15) /*  Pin Controlled by PA15 */
    280. 

  280. #define AT91C_PA15_EMDC     ((unsigned int) AT91C_PIO_PA15) /*   Ethernet MAC Management Data Clock */
    281. 

  281. #define AT91C_PIO_PA14       ((unsigned int) 1 << 14) /*  Pin Controlled by PA14 */
    282. 

  282. #define AT91C_PA14_ERXER    ((unsigned int) AT91C_PIO_PA14) /*   Ethernet MAC Receive Error */
    283. 

  283. #define AT91C_PIO_PA13       ((unsigned int) 1 << 13) /*  Pin Controlled by PA13 */
    284. 

  284. #define AT91C_PA13_ERX1     ((unsigned int) AT91C_PIO_PA13) /*   Ethernet MAC Receive Data 1 */
    285. 

  285. #define AT91C_PIO_PA12       ((unsigned int) 1 << 12) /*  Pin Controlled by PA12 */
    286. 

  286. #define AT91C_PA12_ERX0     ((unsigned int) AT91C_PIO_PA12) /*   Ethernet MAC Receive Data 0 */
    287. 

  287. #define AT91C_PIO_PA11       ((unsigned int) 1 << 11) /*  Pin Controlled by PA11 */
    288. 

  288. #define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /*   Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
    289. 

  289. #define AT91C_PIO_PA10       ((unsigned int) 1 << 10) /*  Pin Controlled by PA10 */
    290. 

  290. #define AT91C_PA10_ETX1     ((unsigned int) AT91C_PIO_PA10) /*   Ethernet MAC Transmit Data 1 */
    291. 

  291. #define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) /*  Pin Controlled by PA9 */
    292. 

  292. #define AT91C_PA9_ETX0     ((unsigned int) AT91C_PIO_PA9) /*   Ethernet MAC Transmit Data 0 */
    293. 

  293. #define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) /*  Pin Controlled by PA8 */
    294. 

  294. #define AT91C_PA8_ETXEN    ((unsigned int) AT91C_PIO_PA8) /*   Ethernet MAC Transmit Enable */
    295. 

  295. #define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) /*  Pin Controlled by PA7 */
    296. 

  296. #define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /*   Ethernet MAC Transmit Clock/Reference Clock */
    297. 

  297. #define AT91C_PIO_PB25       ((unsigned int) 1 << 25) /*  Pin Controlled by PB25 */
    298. 

  298. #define AT91C_PB25_DSR1     ((unsigned int) AT91C_PIO_PB25) /*   USART 1 Data Set ready */
    299. 

  299. #define AT91C_PB25_EF100    ((unsigned int) AT91C_PIO_PB25) /*   Ethernet MAC Force 100 Mbits */
    300. 

  300. #define AT91C_PIO_PB19       ((unsigned int) 1 << 19) /*  Pin Controlled by PB19 */
    301. 

  301. #define AT91C_PB19_DTR1     ((unsigned int) AT91C_PIO_PB19) /*   USART 1 Data Terminal ready */
    302. 

  302. #define AT91C_PB19_ERXCK    ((unsigned int) AT91C_PIO_PB19) /*   Ethernet MAC Receive Clock */
    303. 

  303. #define AT91C_PIO_PB18       ((unsigned int) 1 << 18) /*  Pin Controlled by PB18 */
    304. 

  304. #define AT91C_PB18_RI1      ((unsigned int) AT91C_PIO_PB18) /*   USART 1 Ring Indicator */
    305. 

  305. #define AT91C_PB18_ECOL     ((unsigned int) AT91C_PIO_PB18) /*   Ethernet MAC Collision Detected */
    306. 

  306. #define AT91C_PIO_PB17       ((unsigned int) 1 << 17) /*  Pin Controlled by PB17 */
    307. 

  307. #define AT91C_PB17_RF2      ((unsigned int) AT91C_PIO_PB17) /*   SSC Receive Frame Sync 2 */
    308. 

  308. #define AT91C_PB17_ERXDV    ((unsigned int) AT91C_PIO_PB17) /*   Ethernet MAC Receive Data Valid */
    309. 

  309. #define AT91C_PIO_PB16       ((unsigned int) 1 << 16) /*  Pin Controlled by PB16 */
    310. 

  310. #define AT91C_PB16_RK2      ((unsigned int) AT91C_PIO_PB16) /*   SSC Receive Clock 2 */
    311. 

  311. #define AT91C_PB16_ERX3     ((unsigned int) AT91C_PIO_PB16) /*   Ethernet MAC Receive Data 3 */
    312. 

  312. #define AT91C_PIO_PB15       ((unsigned int) 1 << 15) /*  Pin Controlled by PB15 */
    313. 

  313. #define AT91C_PB15_RD2      ((unsigned int) AT91C_PIO_PB15) /*   SSC Receive Data 2 */
    314. 

  314. #define AT91C_PB15_ERX2     ((unsigned int) AT91C_PIO_PB15) /*   Ethernet MAC Receive Data 2 */
    315. 

  315. #define AT91C_PIO_PB14       ((unsigned int) 1 << 14) /*  Pin Controlled by PB14 */
    316. 

  316. #define AT91C_PB14_TD2      ((unsigned int) AT91C_PIO_PB14) /*   SSC Transmit Data 2 */
    317. 

  317. #define AT91C_PB14_ETXER    ((unsigned int) AT91C_PIO_PB14) /*   Ethernet MAC Transmikt Coding Error */
    318. 

  318. #define AT91C_PIO_PB13       ((unsigned int) 1 << 13) /*  Pin Controlled by PB13 */
    319. 

  319. #define AT91C_PB13_TK2      ((unsigned int) AT91C_PIO_PB13) /*   SSC Transmit Clock 2 */
    320. 

  320. #define AT91C_PB13_ETX3     ((unsigned int) AT91C_PIO_PB13) /*   Ethernet MAC Transmit Data 3 */
    321. 

  321. #define AT91C_PIO_PB12       ((unsigned int) 1 << 12) /*  Pin Controlled by PB12 */
    322. 

  322. #define AT91C_PB12_TF2      ((unsigned int) AT91C_PIO_PB12) /*   SSC Transmit Frame Sync 2 */
    323. 

  323. #define AT91C_PB12_ETX2     ((unsigned int) AT91C_PIO_PB12) /*   Ethernet MAC Transmit Data 2 */
    324. 

  324. 

  325. #define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) /*  (PIOB) Select B Register */
    326. 

  326. #define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFBC000) /*  (EMAC) Base Address */
    327. 

  327. #define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) /*  (PIOB) PIO Disable Register */
    328. 

  328. 

  329. #define 	AT91C_EBI_CS3A_SMC_SmartMedia       ((unsigned int) 0x1 <<  3) /*  (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
    330. 

  330. #define	AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /*  (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
    331. 

  331. #define AT91C_SMC2_DBW_8      ((unsigned int) 0x2 << 13) /*  (SMC2) 8-bit. */
    332. 

  332. #define AT91C_SMC2_WSEN       ((unsigned int) 0x1 <<  7) /*  (SMC2) Wait State Enable */
    333. 

  333. #define AT91C_PIOC_ASR  ((AT91_REG *) 	0xFFFFF870) /*  (PIOC) Select A Register */
    334. 

  334. 

  335. #define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) /*  (TC0) Base Address */
    336. 

  336. #define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) /*  (DBGU) Base Address */
    337. 

  337. #define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) /*  (PIOA) Base Address */
    338. 

  338. #define AT91C_EBI_CSA   ((AT91_REG *) 	0xFFFFFF60) /*  (EBI) Chip Select Assignment Register */
    339. 

  339. #define AT91C_BASE_SMC2      ((AT91PS_SMC2) 	0xFFFFFF70) /*  (SMC2) Base Address */
    340. 

  340. #define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) /*  (US1) Base Address */
    341. 

  341. #define AT91C_TCB0_BMR  ((AT91_REG *) 	0xFFFA00C4) /*  (TCB0) TC Block Mode Register */
    342. 

  342. #define AT91C_TCB0_BCR  ((AT91_REG *) 	0xFFFA00C0) /*  (TCB0) TC Block Control Register */
    343. 

  343. #define AT91C_PIOC_PDR  ((AT91_REG *) 	0xFFFFF804) /*  (PIOC) PIO Disable Register */
    344. 

  344. #define AT91C_PIOC_PER  ((AT91_REG *) 	0xFFFFF800) /*  (PIOC) PIO Enable Register */
    345. 

  345. #define AT91C_PIOC_ODR  ((AT91_REG *) 	0xFFFFF814) /*  (PIOC) Output Disable Registerr */
    346. 

  346. #define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) /*  (PIOB) PIO Enable Register */
    347. 

  347. #define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) /*  (PIOB) Output Disable Registerr */
    348. 

  348. #define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) /*  (PIOB) Pin Data Status Register */
    349. 

  349. #endif
    350.