start.S 6.9 KB

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  1. /*
  2. * armboot - Startup Code for ARM720 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include "config.h"
  26. #include "version.h"
  27. /*
  28. *************************************************************************
  29. *
  30. * Jump vector table as in table 3.1 in [1]
  31. *
  32. *************************************************************************
  33. */
  34. .globl _start
  35. _start: b reset
  36. ldr pc, _undefined_instruction
  37. ldr pc, _software_interrupt
  38. ldr pc, _prefetch_abort
  39. ldr pc, _data_abort
  40. ldr pc, _not_used
  41. ldr pc, _irq
  42. ldr pc, _fiq
  43. _undefined_instruction: .word undefined_instruction
  44. _software_interrupt: .word software_interrupt
  45. _prefetch_abort: .word prefetch_abort
  46. _data_abort: .word data_abort
  47. _not_used: .word not_used
  48. _irq: .word irq
  49. _fiq: .word fiq
  50. .balignl 16,0xdeadbeef
  51. /*
  52. *************************************************************************
  53. *
  54. * Startup Code (reset vector)
  55. *
  56. * do important init only if we don't start from memory!
  57. * relocate armboot to ram
  58. * setup stack
  59. * jump to second stage
  60. *
  61. *************************************************************************
  62. */
  63. /*
  64. * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  65. */
  66. _TEXT_BASE:
  67. .word TEXT_BASE
  68. .globl _armboot_start
  69. _armboot_start:
  70. .word _start
  71. /*
  72. * Note: _armboot_end_data and _armboot_end are defined
  73. * by the (board-dependent) linker script.
  74. * _armboot_end_data is the first usable FLASH address after armboot
  75. */
  76. .globl _armboot_end_data
  77. _armboot_end_data:
  78. .word armboot_end_data
  79. /*
  80. * Note: armboot_end is defined by the (board-dependent) linker script
  81. */
  82. .globl _armboot_end
  83. _armboot_end:
  84. .word armboot_end
  85. /*
  86. * _armboot_real_end is the first usable RAM address behind armboot
  87. * and the various stacks
  88. */
  89. .globl _armboot_real_end
  90. _armboot_real_end:
  91. .word 0x0badc0de
  92. #ifdef CONFIG_USE_IRQ
  93. /* IRQ stack memory (calculated at run-time) */
  94. .globl IRQ_STACK_START
  95. IRQ_STACK_START:
  96. .word 0x0badc0de
  97. /* IRQ stack memory (calculated at run-time) */
  98. .globl FIQ_STACK_START
  99. FIQ_STACK_START:
  100. .word 0x0badc0de
  101. #endif
  102. /*
  103. * the actual reset code
  104. */
  105. reset:
  106. /*
  107. * set the cpu to SVC32 mode
  108. */
  109. mrs r0,cpsr
  110. bic r0,r0,#0x1f
  111. orr r0,r0,#0x13
  112. msr cpsr,r0
  113. /*
  114. * relocate exeception table
  115. */
  116. ldr r0, =_start
  117. ldr r1, =0x0
  118. mov r2, #16
  119. copyex:
  120. subs r2, r2, #1
  121. ldr r3, [r0], #4
  122. str r3, [r1], #4
  123. bne copyex
  124. /*
  125. * we do sys-critical inits only at reboot,
  126. * not when booting from ram!
  127. */
  128. #ifdef CONFIG_INIT_CRITICAL
  129. bl cpu_init_crit
  130. #endif
  131. /* set up the stack */
  132. ldr r0, _armboot_end
  133. add r0, r0, #CONFIG_STACKSIZE
  134. sub sp, r0, #12 /* leave 3 words for abort-stack */
  135. ldr pc,_start_armboot
  136. _start_armboot: .word start_armboot
  137. /*
  138. *************************************************************************
  139. *
  140. * CPU_init_critical registers
  141. *
  142. *************************************************************************
  143. */
  144. cpu_init_crit:
  145. # actually do nothing for now!
  146. mov pc, lr
  147. /*
  148. *************************************************************************
  149. *
  150. * Interrupt handling
  151. *
  152. *************************************************************************
  153. */
  154. @
  155. @ IRQ stack frame.
  156. @
  157. #define S_FRAME_SIZE 72
  158. #define S_OLD_R0 68
  159. #define S_PSR 64
  160. #define S_PC 60
  161. #define S_LR 56
  162. #define S_SP 52
  163. #define S_IP 48
  164. #define S_FP 44
  165. #define S_R10 40
  166. #define S_R9 36
  167. #define S_R8 32
  168. #define S_R7 28
  169. #define S_R6 24
  170. #define S_R5 20
  171. #define S_R4 16
  172. #define S_R3 12
  173. #define S_R2 8
  174. #define S_R1 4
  175. #define S_R0 0
  176. #define MODE_SVC 0x13
  177. #define I_BIT 0x80
  178. /*
  179. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  180. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  181. */
  182. .macro bad_save_user_regs
  183. sub sp, sp, #S_FRAME_SIZE
  184. stmia sp, {r0 - r12} @ Calling r0-r12
  185. add r8, sp, #S_PC
  186. ldr r2, _armboot_end
  187. add r2, r2, #CONFIG_STACKSIZE
  188. sub r2, r2, #8
  189. ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
  190. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  191. add r5, sp, #S_SP
  192. mov r1, lr
  193. stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
  194. mov r0, sp
  195. .endm
  196. .macro irq_save_user_regs
  197. sub sp, sp, #S_FRAME_SIZE
  198. stmia sp, {r0 - r12} @ Calling r0-r12
  199. add r8, sp, #S_PC
  200. stmdb r8, {sp, lr}^ @ Calling SP, LR
  201. str lr, [r8, #0] @ Save calling PC
  202. mrs r6, spsr
  203. str r6, [r8, #4] @ Save CPSR
  204. str r0, [r8, #8] @ Save OLD_R0
  205. mov r0, sp
  206. .endm
  207. .macro irq_restore_user_regs
  208. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  209. mov r0, r0
  210. ldr lr, [sp, #S_PC] @ Get PC
  211. add sp, sp, #S_FRAME_SIZE
  212. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  213. .endm
  214. .macro get_bad_stack
  215. ldr r13, _armboot_end @ setup our mode stack
  216. add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
  217. sub r13, r13, #8
  218. str lr, [r13] @ save caller lr / spsr
  219. mrs lr, spsr
  220. str lr, [r13, #4]
  221. mov r13, #MODE_SVC @ prepare SVC-Mode
  222. msr spsr_c, r13
  223. mov lr, pc
  224. movs pc, lr
  225. .endm
  226. .macro get_irq_stack @ setup IRQ stack
  227. ldr sp, IRQ_STACK_START
  228. .endm
  229. .macro get_fiq_stack @ setup FIQ stack
  230. ldr sp, FIQ_STACK_START
  231. .endm
  232. /*
  233. * exception handlers
  234. */
  235. .align 5
  236. undefined_instruction:
  237. get_bad_stack
  238. bad_save_user_regs
  239. bl do_undefined_instruction
  240. .align 5
  241. software_interrupt:
  242. get_bad_stack
  243. bad_save_user_regs
  244. bl do_software_interrupt
  245. .align 5
  246. prefetch_abort:
  247. get_bad_stack
  248. bad_save_user_regs
  249. bl do_prefetch_abort
  250. .align 5
  251. data_abort:
  252. get_bad_stack
  253. bad_save_user_regs
  254. bl do_data_abort
  255. .align 5
  256. not_used:
  257. get_bad_stack
  258. bad_save_user_regs
  259. bl do_not_used
  260. #ifdef CONFIG_USE_IRQ
  261. .align 5
  262. irq:
  263. get_irq_stack
  264. irq_save_user_regs
  265. bl do_irq
  266. irq_restore_user_regs
  267. .align 5
  268. fiq:
  269. get_fiq_stack
  270. /* someone ought to write a more effiction fiq_save_user_regs */
  271. irq_save_user_regs
  272. bl do_fiq
  273. irq_restore_user_regs
  274. #else
  275. .align 5
  276. irq:
  277. get_bad_stack
  278. bad_save_user_regs
  279. bl do_irq
  280. .align 5
  281. fiq:
  282. get_bad_stack
  283. bad_save_user_regs
  284. bl do_fiq
  285. #endif
  286. .align 5
  287. .globl reset_cpu
  288. reset_cpu:
  289. mov pc, r0