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arch-exynos
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clock.h

clock.h 25 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2010 Samsung Electronics
    3. 

  3.  * Minkyu Kang <mk7.kang@samsung.com>
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or
    6. 

  6.  * modify it under the terms of the GNU General Public License as
    7. 

  7.  * published by the Free Software Foundation; either version 2 of
    8. 

  8.  * the License, or (at your option) any later version.
    9. 

  9.  *
    10. 

  10.  * This program is distributed in the hope that it will be useful,
    11. 

  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    12. 

  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13. 

  13.  * GNU General Public License for more details.
    14. 

  14.  *
    15. 

  15.  * You should have received a copy of the GNU General Public License
    16. 

  16.  * along with this program; if not, write to the Free Software
    17. 

  17.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    18. 

  18.  * MA 02111-1307 USA
    19. 

  19.  *
    20. 

  20.  */
    21. 

  21. 

  22. #ifndef __ASM_ARM_ARCH_CLOCK_H_
    23. 

  23. #define __ASM_ARM_ARCH_CLOCK_H_
    24. 

  24. 

  25. #ifndef __ASSEMBLY__
    26. 

  26. struct exynos4_clock {
    27. 

  27. 	unsigned char	res1[0x4200];
    28. 

  28. 	unsigned int	src_leftbus;
    29. 

  29. 	unsigned char	res2[0x1fc];
    30. 

  30. 	unsigned int	mux_stat_leftbus;
    31. 

  31. 	unsigned char	res4[0xfc];
    32. 

  32. 	unsigned int	div_leftbus;
    33. 

  33. 	unsigned char	res5[0xfc];
    34. 

  34. 	unsigned int	div_stat_leftbus;
    35. 

  35. 	unsigned char	res6[0x1fc];
    36. 

  36. 	unsigned int	gate_ip_leftbus;
    37. 

  37. 	unsigned char	res7[0x1fc];
    38. 

  38. 	unsigned int	clkout_leftbus;
    39. 

  39. 	unsigned int	clkout_leftbus_div_stat;
    40. 

  40. 	unsigned char	res8[0x37f8];
    41. 

  41. 	unsigned int	src_rightbus;
    42. 

  42. 	unsigned char	res9[0x1fc];
    43. 

  43. 	unsigned int	mux_stat_rightbus;
    44. 

  44. 	unsigned char	res10[0xfc];
    45. 

  45. 	unsigned int	div_rightbus;
    46. 

  46. 	unsigned char	res11[0xfc];
    47. 

  47. 	unsigned int	div_stat_rightbus;
    48. 

  48. 	unsigned char	res12[0x1fc];
    49. 

  49. 	unsigned int	gate_ip_rightbus;
    50. 

  50. 	unsigned char	res13[0x1fc];
    51. 

  51. 	unsigned int	clkout_rightbus;
    52. 

  52. 	unsigned int	clkout_rightbus_div_stat;
    53. 

  53. 	unsigned char	res14[0x3608];
    54. 

  54. 	unsigned int	epll_lock;
    55. 

  55. 	unsigned char	res15[0xc];
    56. 

  56. 	unsigned int	vpll_lock;
    57. 

  57. 	unsigned char	res16[0xec];
    58. 

  58. 	unsigned int	epll_con0;
    59. 

  59. 	unsigned int	epll_con1;
    60. 

  60. 	unsigned char	res17[0x8];
    61. 

  61. 	unsigned int	vpll_con0;
    62. 

  62. 	unsigned int	vpll_con1;
    63. 

  63. 	unsigned char	res18[0xe8];
    64. 

  64. 	unsigned int	src_top0;
    65. 

  65. 	unsigned int	src_top1;
    66. 

  66. 	unsigned char	res19[0x8];
    67. 

  67. 	unsigned int	src_cam;
    68. 

  68. 	unsigned int	src_tv;
    69. 

  69. 	unsigned int	src_mfc;
    70. 

  70. 	unsigned int	src_g3d;
    71. 

  71. 	unsigned int	src_image;
    72. 

  72. 	unsigned int	src_lcd0;
    73. 

  73. 	unsigned int	src_lcd1;
    74. 

  74. 	unsigned int	src_maudio;
    75. 

  75. 	unsigned int	src_fsys;
    76. 

  76. 	unsigned char	res20[0xc];
    77. 

  77. 	unsigned int	src_peril0;
    78. 

  78. 	unsigned int	src_peril1;
    79. 

  79. 	unsigned char	res21[0xb8];
    80. 

  80. 	unsigned int	src_mask_top;
    81. 

  81. 	unsigned char	res22[0xc];
    82. 

  82. 	unsigned int	src_mask_cam;
    83. 

  83. 	unsigned int	src_mask_tv;
    84. 

  84. 	unsigned char	res23[0xc];
    85. 

  85. 	unsigned int	src_mask_lcd0;
    86. 

  86. 	unsigned int	src_mask_lcd1;
    87. 

  87. 	unsigned int	src_mask_maudio;
    88. 

  88. 	unsigned int	src_mask_fsys;
    89. 

  89. 	unsigned char	res24[0xc];
    90. 

  90. 	unsigned int	src_mask_peril0;
    91. 

  91. 	unsigned int	src_mask_peril1;
    92. 

  92. 	unsigned char	res25[0xb8];
    93. 

  93. 	unsigned int	mux_stat_top;
    94. 

  94. 	unsigned char	res26[0x14];
    95. 

  95. 	unsigned int	mux_stat_mfc;
    96. 

  96. 	unsigned int	mux_stat_g3d;
    97. 

  97. 	unsigned int	mux_stat_image;
    98. 

  98. 	unsigned char	res27[0xdc];
    99. 

  99. 	unsigned int	div_top;
    100. 

  100. 	unsigned char	res28[0xc];
    101. 

  101. 	unsigned int	div_cam;
    102. 

  102. 	unsigned int	div_tv;
    103. 

  103. 	unsigned int	div_mfc;
    104. 

  104. 	unsigned int	div_g3d;
    105. 

  105. 	unsigned int	div_image;
    106. 

  106. 	unsigned int	div_lcd0;
    107. 

  107. 	unsigned int	div_lcd1;
    108. 

  108. 	unsigned int	div_maudio;
    109. 

  109. 	unsigned int	div_fsys0;
    110. 

  110. 	unsigned int	div_fsys1;
    111. 

  111. 	unsigned int	div_fsys2;
    112. 

  112. 	unsigned int	div_fsys3;
    113. 

  113. 	unsigned int	div_peril0;
    114. 

  114. 	unsigned int	div_peril1;
    115. 

  115. 	unsigned int	div_peril2;
    116. 

  116. 	unsigned int	div_peril3;
    117. 

  117. 	unsigned int	div_peril4;
    118. 

  118. 	unsigned int	div_peril5;
    119. 

  119. 	unsigned char	res29[0x18];
    120. 

  120. 	unsigned int	div2_ratio;
    121. 

  121. 	unsigned char	res30[0x8c];
    122. 

  122. 	unsigned int	div_stat_top;
    123. 

  123. 	unsigned char	res31[0xc];
    124. 

  124. 	unsigned int	div_stat_cam;
    125. 

  125. 	unsigned int	div_stat_tv;
    126. 

  126. 	unsigned int	div_stat_mfc;
    127. 

  127. 	unsigned int	div_stat_g3d;
    128. 

  128. 	unsigned int	div_stat_image;
    129. 

  129. 	unsigned int	div_stat_lcd0;
    130. 

  130. 	unsigned int	div_stat_lcd1;
    131. 

  131. 	unsigned int	div_stat_maudio;
    132. 

  132. 	unsigned int	div_stat_fsys0;
    133. 

  133. 	unsigned int	div_stat_fsys1;
    134. 

  134. 	unsigned int	div_stat_fsys2;
    135. 

  135. 	unsigned int	div_stat_fsys3;
    136. 

  136. 	unsigned int	div_stat_peril0;
    137. 

  137. 	unsigned int	div_stat_peril1;
    138. 

  138. 	unsigned int	div_stat_peril2;
    139. 

  139. 	unsigned int	div_stat_peril3;
    140. 

  140. 	unsigned int	div_stat_peril4;
    141. 

  141. 	unsigned int	div_stat_peril5;
    142. 

  142. 	unsigned char	res32[0x18];
    143. 

  143. 	unsigned int	div2_stat;
    144. 

  144. 	unsigned char	res33[0x29c];
    145. 

  145. 	unsigned int	gate_ip_cam;
    146. 

  146. 	unsigned int	gate_ip_tv;
    147. 

  147. 	unsigned int	gate_ip_mfc;
    148. 

  148. 	unsigned int	gate_ip_g3d;
    149. 

  149. 	unsigned int	gate_ip_image;
    150. 

  150. 	unsigned int	gate_ip_lcd0;
    151. 

  151. 	unsigned int	gate_ip_lcd1;
    152. 

  152. 	unsigned char	res34[0x4];
    153. 

  153. 	unsigned int	gate_ip_fsys;
    154. 

  154. 	unsigned char	res35[0x8];
    155. 

  155. 	unsigned int	gate_ip_gps;
    156. 

  156. 	unsigned int	gate_ip_peril;
    157. 

  157. 	unsigned char	res36[0xc];
    158. 

  158. 	unsigned int	gate_ip_perir;
    159. 

  159. 	unsigned char	res37[0xc];
    160. 

  160. 	unsigned int	gate_block;
    161. 

  161. 	unsigned char	res38[0x8c];
    162. 

  162. 	unsigned int	clkout_cmu_top;
    163. 

  163. 	unsigned int	clkout_cmu_top_div_stat;
    164. 

  164. 	unsigned char	res39[0x37f8];
    165. 

  165. 	unsigned int	src_dmc;
    166. 

  166. 	unsigned char	res40[0xfc];
    167. 

  167. 	unsigned int	src_mask_dmc;
    168. 

  168. 	unsigned char	res41[0xfc];
    169. 

  169. 	unsigned int	mux_stat_dmc;
    170. 

  170. 	unsigned char	res42[0xfc];
    171. 

  171. 	unsigned int	div_dmc0;
    172. 

  172. 	unsigned int	div_dmc1;
    173. 

  173. 	unsigned char	res43[0xf8];
    174. 

  174. 	unsigned int	div_stat_dmc0;
    175. 

  175. 	unsigned int	div_stat_dmc1;
    176. 

  176. 	unsigned char	res44[0x2f8];
    177. 

  177. 	unsigned int	gate_ip_dmc;
    178. 

  178. 	unsigned char	res45[0xfc];
    179. 

  179. 	unsigned int	clkout_cmu_dmc;
    180. 

  180. 	unsigned int	clkout_cmu_dmc_div_stat;
    181. 

  181. 	unsigned char	res46[0x5f8];
    182. 

  182. 	unsigned int	dcgidx_map0;
    183. 

  183. 	unsigned int	dcgidx_map1;
    184. 

  184. 	unsigned int	dcgidx_map2;
    185. 

  185. 	unsigned char	res47[0x14];
    186. 

  186. 	unsigned int	dcgperf_map0;
    187. 

  187. 	unsigned int	dcgperf_map1;
    188. 

  188. 	unsigned char	res48[0x18];
    189. 

  189. 	unsigned int	dvcidx_map;
    190. 

  190. 	unsigned char	res49[0x1c];
    191. 

  191. 	unsigned int	freq_cpu;
    192. 

  192. 	unsigned int	freq_dpm;
    193. 

  193. 	unsigned char	res50[0x18];
    194. 

  194. 	unsigned int	dvsemclk_en;
    195. 

  195. 	unsigned int	maxperf;
    196. 

  196. 	unsigned char	res51[0x2f78];
    197. 

  197. 	unsigned int	apll_lock;
    198. 

  198. 	unsigned char	res52[0x4];
    199. 

  199. 	unsigned int	mpll_lock;
    200. 

  200. 	unsigned char	res53[0xf4];
    201. 

  201. 	unsigned int	apll_con0;
    202. 

  202. 	unsigned int	apll_con1;
    203. 

  203. 	unsigned int	mpll_con0;
    204. 

  204. 	unsigned int	mpll_con1;
    205. 

  205. 	unsigned char	res54[0xf0];
    206. 

  206. 	unsigned int	src_cpu;
    207. 

  207. 	unsigned char	res55[0x1fc];
    208. 

  208. 	unsigned int	mux_stat_cpu;
    209. 

  209. 	unsigned char	res56[0xfc];
    210. 

  210. 	unsigned int	div_cpu0;
    211. 

  211. 	unsigned int	div_cpu1;
    212. 

  212. 	unsigned char	res57[0xf8];
    213. 

  213. 	unsigned int	div_stat_cpu0;
    214. 

  214. 	unsigned int	div_stat_cpu1;
    215. 

  215. 	unsigned char	res58[0x3f8];
    216. 

  216. 	unsigned int	clkout_cmu_cpu;
    217. 

  217. 	unsigned int	clkout_cmu_cpu_div_stat;
    218. 

  218. 	unsigned char	res59[0x5f8];
    219. 

  219. 	unsigned int	armclk_stopctrl;
    220. 

  220. 	unsigned int	atclk_stopctrl;
    221. 

  221. 	unsigned char	res60[0x8];
    222. 

  222. 	unsigned int	parityfail_status;
    223. 

  223. 	unsigned int	parityfail_clear;
    224. 

  224. 	unsigned char	res61[0xe8];
    225. 

  225. 	unsigned int	apll_con0_l8;
    226. 

  226. 	unsigned int	apll_con0_l7;
    227. 

  227. 	unsigned int	apll_con0_l6;
    228. 

  228. 	unsigned int	apll_con0_l5;
    229. 

  229. 	unsigned int	apll_con0_l4;
    230. 

  230. 	unsigned int	apll_con0_l3;
    231. 

  231. 	unsigned int	apll_con0_l2;
    232. 

  232. 	unsigned int	apll_con0_l1;
    233. 

  233. 	unsigned int	iem_control;
    234. 

  234. 	unsigned char	res62[0xdc];
    235. 

  235. 	unsigned int	apll_con1_l8;
    236. 

  236. 	unsigned int	apll_con1_l7;
    237. 

  237. 	unsigned int	apll_con1_l6;
    238. 

  238. 	unsigned int	apll_con1_l5;
    239. 

  239. 	unsigned int	apll_con1_l4;
    240. 

  240. 	unsigned int	apll_con1_l3;
    241. 

  241. 	unsigned int	apll_con1_l2;
    242. 

  242. 	unsigned int	apll_con1_l1;
    243. 

  243. 	unsigned char	res63[0xe0];
    244. 

  244. 	unsigned int	div_iem_l8;
    245. 

  245. 	unsigned int	div_iem_l7;
    246. 

  246. 	unsigned int	div_iem_l6;
    247. 

  247. 	unsigned int	div_iem_l5;
    248. 

  248. 	unsigned int	div_iem_l4;
    249. 

  249. 	unsigned int	div_iem_l3;
    250. 

  250. 	unsigned int	div_iem_l2;
    251. 

  251. 	unsigned int	div_iem_l1;
    252. 

  252. };
    253. 

  253. 

  254. struct exynos4x12_clock {
    255. 

  255. 	unsigned char	res1[0x4200];
    256. 

  256. 	unsigned int	src_leftbus;
    257. 

  257. 	unsigned char	res2[0x1fc];
    258. 

  258. 	unsigned int	mux_stat_leftbus;
    259. 

  259. 	unsigned char	res3[0xfc];
    260. 

  260. 	unsigned int	div_leftbus;
    261. 

  261. 	unsigned char	res4[0xfc];
    262. 

  262. 	unsigned int	div_stat_leftbus;
    263. 

  263. 	unsigned char	res5[0x1fc];
    264. 

  264. 	unsigned int	gate_ip_leftbus;
    265. 

  265. 	unsigned char	res6[0x12c];
    266. 

  266. 	unsigned int	gate_ip_image;
    267. 

  267. 	unsigned char	res7[0xcc];
    268. 

  268. 	unsigned int	clkout_leftbus;
    269. 

  269. 	unsigned int	clkout_leftbus_div_stat;
    270. 

  270. 	unsigned char	res8[0x37f8];
    271. 

  271. 	unsigned int	src_rightbus;
    272. 

  272. 	unsigned char	res9[0x1fc];
    273. 

  273. 	unsigned int	mux_stat_rightbus;
    274. 

  274. 	unsigned char	res10[0xfc];
    275. 

  275. 	unsigned int	div_rightbus;
    276. 

  276. 	unsigned char	res11[0xfc];
    277. 

  277. 	unsigned int	div_stat_rightbus;
    278. 

  278. 	unsigned char	res12[0x1fc];
    279. 

  279. 	unsigned int	gate_ip_rightbus;
    280. 

  280. 	unsigned char	res13[0x15c];
    281. 

  281. 	unsigned int	gate_ip_perir;
    282. 

  282. 	unsigned char	res14[0x9c];
    283. 

  283. 	unsigned int	clkout_rightbus;
    284. 

  284. 	unsigned int	clkout_rightbus_div_stat;
    285. 

  285. 	unsigned char	res15[0x3608];
    286. 

  286. 	unsigned int	epll_lock;
    287. 

  287. 	unsigned char	res16[0xc];
    288. 

  288. 	unsigned int	vpll_lock;
    289. 

  289. 	unsigned char	res17[0xec];
    290. 

  290. 	unsigned int	epll_con0;
    291. 

  291. 	unsigned int	epll_con1;
    292. 

  292. 	unsigned int	epll_con2;
    293. 

  293. 	unsigned char	res18[0x4];
    294. 

  294. 	unsigned int	vpll_con0;
    295. 

  295. 	unsigned int	vpll_con1;
    296. 

  296. 	unsigned int	vpll_con2;
    297. 

  297. 	unsigned char	res19[0xe4];
    298. 

  298. 	unsigned int	src_top0;
    299. 

  299. 	unsigned int	src_top1;
    300. 

  300. 	unsigned char	res20[0x8];
    301. 

  301. 	unsigned int	src_cam;
    302. 

  302. 	unsigned int	src_tv;
    303. 

  303. 	unsigned int	src_mfc;
    304. 

  304. 	unsigned int	src_g3d;
    305. 

  305. 	unsigned char	res21[0x4];
    306. 

  306. 	unsigned int	src_lcd;
    307. 

  307. 	unsigned int	src_isp;
    308. 

  308. 	unsigned int	src_maudio;
    309. 

  309. 	unsigned int	src_fsys;
    310. 

  310. 	unsigned char	res22[0xc];
    311. 

  311. 	unsigned int	src_peril0;
    312. 

  312. 	unsigned int	src_peril1;
    313. 

  313. 	unsigned int	src_cam1;
    314. 

  314. 	unsigned char	res23[0xb4];
    315. 

  315. 	unsigned int	src_mask_top;
    316. 

  316. 	unsigned char	res24[0xc];
    317. 

  317. 	unsigned int	src_mask_cam;
    318. 

  318. 	unsigned int	src_mask_tv;
    319. 

  319. 	unsigned char	res25[0xc];
    320. 

  320. 	unsigned int	src_mask_lcd;
    321. 

  321. 	unsigned int	src_mask_isp;
    322. 

  322. 	unsigned int	src_mask_maudio;
    323. 

  323. 	unsigned int	src_mask_fsys;
    324. 

  324. 	unsigned char	res26[0xc];
    325. 

  325. 	unsigned int	src_mask_peril0;
    326. 

  326. 	unsigned int	src_mask_peril1;
    327. 

  327. 	unsigned char	res27[0xb8];
    328. 

  328. 	unsigned int	mux_stat_top0;
    329. 

  329. 	unsigned int	mux_stat_top1;
    330. 

  330. 	unsigned char	res28[0x10];
    331. 

  331. 	unsigned int	mux_stat_mfc;
    332. 

  332. 	unsigned int	mux_stat_g3d;
    333. 

  333. 	unsigned char	res29[0x28];
    334. 

  334. 	unsigned int	mux_stat_cam1;
    335. 

  335. 	unsigned char	res30[0xb4];
    336. 

  336. 	unsigned int	div_top;
    337. 

  337. 	unsigned char	res31[0xc];
    338. 

  338. 	unsigned int	div_cam;
    339. 

  339. 	unsigned int	div_tv;
    340. 

  340. 	unsigned int	div_mfc;
    341. 

  341. 	unsigned int	div_g3d;
    342. 

  342. 	unsigned char	res32[0x4];
    343. 

  343. 	unsigned int	div_lcd;
    344. 

  344. 	unsigned int	div_isp;
    345. 

  345. 	unsigned int	div_maudio;
    346. 

  346. 	unsigned int	div_fsys0;
    347. 

  347. 	unsigned int	div_fsys1;
    348. 

  348. 	unsigned int	div_fsys2;
    349. 

  349. 	unsigned int	div_fsys3;
    350. 

  350. 	unsigned int	div_peril0;
    351. 

  351. 	unsigned int	div_peril1;
    352. 

  352. 	unsigned int	div_peril2;
    353. 

  353. 	unsigned int	div_peril3;
    354. 

  354. 	unsigned int	div_peril4;
    355. 

  355. 	unsigned int	div_peril5;
    356. 

  356. 	unsigned int	div_cam1;
    357. 

  357. 	unsigned char	res33[0x14];
    358. 

  358. 	unsigned int	div2_ratio;
    359. 

  359. 	unsigned char	res34[0x8c];
    360. 

  360. 	unsigned int	div_stat_top;
    361. 

  361. 	unsigned char	res35[0xc];
    362. 

  362. 	unsigned int	div_stat_cam;
    363. 

  363. 	unsigned int	div_stat_tv;
    364. 

  364. 	unsigned int	div_stat_mfc;
    365. 

  365. 	unsigned int	div_stat_g3d;
    366. 

  366. 	unsigned char	res36[0x4];
    367. 

  367. 	unsigned int	div_stat_lcd;
    368. 

  368. 	unsigned int	div_stat_isp;
    369. 

  369. 	unsigned int	div_stat_maudio;
    370. 

  370. 	unsigned int	div_stat_fsys0;
    371. 

  371. 	unsigned int	div_stat_fsys1;
    372. 

  372. 	unsigned int	div_stat_fsys2;
    373. 

  373. 	unsigned int	div_stat_fsys3;
    374. 

  374. 	unsigned int	div_stat_peril0;
    375. 

  375. 	unsigned int	div_stat_peril1;
    376. 

  376. 	unsigned int	div_stat_peril2;
    377. 

  377. 	unsigned int	div_stat_peril3;
    378. 

  378. 	unsigned int	div_stat_peril4;
    379. 

  379. 	unsigned int	div_stat_peril5;
    380. 

  380. 	unsigned int	div_stat_cam1;
    381. 

  381. 	unsigned char	res37[0x14];
    382. 

  382. 	unsigned int	div2_stat;
    383. 

  383. 	unsigned char	res38[0x29c];
    384. 

  384. 	unsigned int	gate_ip_cam;
    385. 

  385. 	unsigned int	gate_ip_tv;
    386. 

  386. 	unsigned int	gate_ip_mfc;
    387. 

  387. 	unsigned int	gate_ip_g3d;
    388. 

  388. 	unsigned char	res39[0x4];
    389. 

  389. 	unsigned int	gate_ip_lcd;
    390. 

  390. 	unsigned int	gate_ip_isp;
    391. 

  391. 	unsigned char	res40[0x4];
    392. 

  392. 	unsigned int	gate_ip_fsys;
    393. 

  393. 	unsigned char	res41[0x8];
    394. 

  394. 	unsigned int	gate_ip_gps;
    395. 

  395. 	unsigned int	gate_ip_peril;
    396. 

  396. 	unsigned char	res42[0xc];
    397. 

  397. 	unsigned char	res43[0x4];
    398. 

  398. 	unsigned char	res44[0xc];
    399. 

  399. 	unsigned int	gate_block;
    400. 

  400. 	unsigned char	res45[0x8c];
    401. 

  401. 	unsigned int	clkout_cmu_top;
    402. 

  402. 	unsigned int	clkout_cmu_top_div_stat;
    403. 

  403. 	unsigned char	res46[0x3600];
    404. 

  404. 	unsigned int	mpll_lock;
    405. 

  405. 	unsigned char	res47[0xfc];
    406. 

  406. 	unsigned int	mpll_con0;
    407. 

  407. 	unsigned int	mpll_con1;
    408. 

  408. 	unsigned char	res48[0xf0];
    409. 

  409. 	unsigned int	src_dmc;
    410. 

  410. 	unsigned char	res49[0xfc];
    411. 

  411. 	unsigned int	src_mask_dmc;
    412. 

  412. 	unsigned char	res50[0xfc];
    413. 

  413. 	unsigned int	mux_stat_dmc;
    414. 

  414. 	unsigned char	res51[0xfc];
    415. 

  415. 	unsigned int	div_dmc0;
    416. 

  416. 	unsigned int	div_dmc1;
    417. 

  417. 	unsigned char	res52[0xf8];
    418. 

  418. 	unsigned int	div_stat_dmc0;
    419. 

  419. 	unsigned int	div_stat_dmc1;
    420. 

  420. 	unsigned char	res53[0xf8];
    421. 

  421. 	unsigned int	gate_bus_dmc0;
    422. 

  422. 	unsigned int	gate_bus_dmc1;
    423. 

  423. 	unsigned char	res54[0x1f8];
    424. 

  424. 	unsigned int	gate_ip_dmc0;
    425. 

  425. 	unsigned int	gate_ip_dmc1;
    426. 

  426. 	unsigned char	res55[0xf8];
    427. 

  427. 	unsigned int	clkout_cmu_dmc;
    428. 

  428. 	unsigned int	clkout_cmu_dmc_div_stat;
    429. 

  429. 	unsigned char	res56[0x5f8];
    430. 

  430. 	unsigned int	dcgidx_map0;
    431. 

  431. 	unsigned int	dcgidx_map1;
    432. 

  432. 	unsigned int	dcgidx_map2;
    433. 

  433. 	unsigned char	res57[0x14];
    434. 

  434. 	unsigned int	dcgperf_map0;
    435. 

  435. 	unsigned int	dcgperf_map1;
    436. 

  436. 	unsigned char	res58[0x18];
    437. 

  437. 	unsigned int	dvcidx_map;
    438. 

  438. 	unsigned char	res59[0x1c];
    439. 

  439. 	unsigned int	freq_cpu;
    440. 

  440. 	unsigned int	freq_dpm;
    441. 

  441. 	unsigned char	res60[0x18];
    442. 

  442. 	unsigned int	dvsemclk_en;
    443. 

  443. 	unsigned int	maxperf;
    444. 

  444. 	unsigned char	res61[0x8];
    445. 

  445. 	unsigned int	dmc_freq_ctrl;
    446. 

  446. 	unsigned int	dmc_pause_ctrl;
    447. 

  447. 	unsigned int	dddrphy_lock_ctrl;
    448. 

  448. 	unsigned int	c2c_state;
    449. 

  449. 	unsigned char	res62[0x2f60];
    450. 

  450. 	unsigned int	apll_lock;
    451. 

  451. 	unsigned char	res63[0x8];
    452. 

  452. 	unsigned char	res64[0xf4];
    453. 

  453. 	unsigned int	apll_con0;
    454. 

  454. 	unsigned int	apll_con1;
    455. 

  455. 	unsigned char	res65[0xf8];
    456. 

  456. 	unsigned int	src_cpu;
    457. 

  457. 	unsigned char	res66[0x1fc];
    458. 

  458. 	unsigned int	mux_stat_cpu;
    459. 

  459. 	unsigned char	res67[0xfc];
    460. 

  460. 	unsigned int	div_cpu0;
    461. 

  461. 	unsigned int	div_cpu1;
    462. 

  462. 	unsigned char	res68[0xf8];
    463. 

  463. 	unsigned int	div_stat_cpu0;
    464. 

  464. 	unsigned int	div_stat_cpu1;
    465. 

  465. 	unsigned char	res69[0x2f8];
    466. 

  466. 	unsigned int	clk_gate_ip_cpu;
    467. 

  467. 	unsigned char	res70[0xfc];
    468. 

  468. 	unsigned int	clkout_cmu_cpu;
    469. 

  469. 	unsigned int	clkout_cmu_cpu_div_stat;
    470. 

  470. 	unsigned char	res71[0x5f8];
    471. 

  471. 	unsigned int	armclk_stopctrl;
    472. 

  472. 	unsigned int	atclk_stopctrl;
    473. 

  473. 	unsigned char	res72[0x10];
    474. 

  474. 	unsigned char	res73[0x8];
    475. 

  475. 	unsigned int	pwr_ctrl;
    476. 

  476. 	unsigned int	pwr_ctrl2;
    477. 

  477. 	unsigned char	res74[0xd8];
    478. 

  478. 	unsigned int	apll_con0_l8;
    479. 

  479. 	unsigned int	apll_con0_l7;
    480. 

  480. 	unsigned int	apll_con0_l6;
    481. 

  481. 	unsigned int	apll_con0_l5;
    482. 

  482. 	unsigned int	apll_con0_l4;
    483. 

  483. 	unsigned int	apll_con0_l3;
    484. 

  484. 	unsigned int	apll_con0_l2;
    485. 

  485. 	unsigned int	apll_con0_l1;
    486. 

  486. 	unsigned int	iem_control;
    487. 

  487. 	unsigned char	res75[0xdc];
    488. 

  488. 	unsigned int	apll_con1_l8;
    489. 

  489. 	unsigned int	apll_con1_l7;
    490. 

  490. 	unsigned int	apll_con1_l6;
    491. 

  491. 	unsigned int	apll_con1_l5;
    492. 

  492. 	unsigned int	apll_con1_l4;
    493. 

  493. 	unsigned int	apll_con1_l3;
    494. 

  494. 	unsigned int	apll_con1_l2;
    495. 

  495. 	unsigned int	apll_con1_l1;
    496. 

  496. 	unsigned char	res76[0xe0];
    497. 

  497. 	unsigned int	div_iem_l8;
    498. 

  498. 	unsigned int	div_iem_l7;
    499. 

  499. 	unsigned int	div_iem_l6;
    500. 

  500. 	unsigned int	div_iem_l5;
    501. 

  501. 	unsigned int	div_iem_l4;
    502. 

  502. 	unsigned int	div_iem_l3;
    503. 

  503. 	unsigned int	div_iem_l2;
    504. 

  504. 	unsigned int	div_iem_l1;
    505. 

  505. 	unsigned char	res77[0xe0];
    506. 

  506. 	unsigned int	l2_status;
    507. 

  507. 	unsigned char	res78[0xc];
    508. 

  508. 	unsigned int	cpu_status;
    509. 

  509. 	unsigned char	res79[0xc];
    510. 

  510. 	unsigned int	ptm_status;
    511. 

  511. 	unsigned char	res80[0x2edc];
    512. 

  512. 	unsigned int	div_isp0;
    513. 

  513. 	unsigned int	div_isp1;
    514. 

  514. 	unsigned char	res81[0xf8];
    515. 

  515. 	unsigned int	div_stat_isp0;
    516. 

  516. 	unsigned int	div_stat_isp1;
    517. 

  517. 	unsigned char	res82[0x3f8];
    518. 

  518. 	unsigned int	gate_ip_isp0;
    519. 

  519. 	unsigned int	gate_ip_isp1;
    520. 

  520. 	unsigned char	res83[0x1f8];
    521. 

  521. 	unsigned int	clkout_cmu_isp;
    522. 

  522. 	unsigned int	clkout_cmu_ispd_div_stat;
    523. 

  523. 	unsigned char	res84[0xf8];
    524. 

  524. 	unsigned int	cmu_isp_spar0;
    525. 

  525. 	unsigned int	cmu_isp_spar1;
    526. 

  526. 	unsigned int	cmu_isp_spar2;
    527. 

  527. 	unsigned int	cmu_isp_spar3;
    528. 

  528. };
    529. 

  529. 

  530. struct exynos5_clock {
    531. 

  531. 	unsigned int	apll_lock;
    532. 

  532. 	unsigned char	res1[0xfc];
    533. 

  533. 	unsigned int	apll_con0;
    534. 

  534. 	unsigned int	apll_con1;
    535. 

  535. 	unsigned char	res2[0xf8];
    536. 

  536. 	unsigned int	src_cpu;
    537. 

  537. 	unsigned char	res3[0x1fc];
    538. 

  538. 	unsigned int	mux_stat_cpu;
    539. 

  539. 	unsigned char	res4[0xfc];
    540. 

  540. 	unsigned int	div_cpu0;
    541. 

  541. 	unsigned int	div_cpu1;
    542. 

  542. 	unsigned char	res5[0xf8];
    543. 

  543. 	unsigned int	div_stat_cpu0;
    544. 

  544. 	unsigned int	div_stat_cpu1;
    545. 

  545. 	unsigned char	res6[0x1f8];
    546. 

  546. 	unsigned int	gate_sclk_cpu;
    547. 

  547. 	unsigned char	res7[0x1fc];
    548. 

  548. 	unsigned int	clkout_cmu_cpu;
    549. 

  549. 	unsigned int	clkout_cmu_cpu_div_stat;
    550. 

  550. 	unsigned char	res8[0x5f8];
    551. 

  551. 	unsigned int	armclk_stopctrl;
    552. 

  552. 	unsigned char	res9[0x0c];
    553. 

  553. 	unsigned int	parityfail_status;
    554. 

  554. 	unsigned int	parityfail_clear;
    555. 

  555. 	unsigned char	res10[0x8];
    556. 

  556. 	unsigned int	pwr_ctrl;
    557. 

  557. 	unsigned int	pwr_ctr2;
    558. 

  558. 	unsigned char	res11[0xd8];
    559. 

  559. 	unsigned int	apll_con0_l8;
    560. 

  560. 	unsigned int	apll_con0_l7;
    561. 

  561. 	unsigned int	apll_con0_l6;
    562. 

  562. 	unsigned int	apll_con0_l5;
    563. 

  563. 	unsigned int	apll_con0_l4;
    564. 

  564. 	unsigned int	apll_con0_l3;
    565. 

  565. 	unsigned int	apll_con0_l2;
    566. 

  566. 	unsigned int	apll_con0_l1;
    567. 

  567. 	unsigned int	iem_control;
    568. 

  568. 	unsigned char	res12[0xdc];
    569. 

  569. 	unsigned int	apll_con1_l8;
    570. 

  570. 	unsigned int	apll_con1_l7;
    571. 

  571. 	unsigned int	apll_con1_l6;
    572. 

  572. 	unsigned int	apll_con1_l5;
    573. 

  573. 	unsigned int	apll_con1_l4;
    574. 

  574. 	unsigned int	apll_con1_l3;
    575. 

  575. 	unsigned int	apll_con1_l2;
    576. 

  576. 	unsigned int	apll_con1_l1;
    577. 

  577. 	unsigned char	res13[0xe0];
    578. 

  578. 	unsigned int	div_iem_l8;
    579. 

  579. 	unsigned int	div_iem_l7;
    580. 

  580. 	unsigned int	div_iem_l6;
    581. 

  581. 	unsigned int	div_iem_l5;
    582. 

  582. 	unsigned int	div_iem_l4;
    583. 

  583. 	unsigned int	div_iem_l3;
    584. 

  584. 	unsigned int	div_iem_l2;
    585. 

  585. 	unsigned int	div_iem_l1;
    586. 

  586. 	unsigned char	res14[0x2ce0];
    587. 

  587. 	unsigned int	mpll_lock;
    588. 

  588. 	unsigned char	res15[0xfc];
    589. 

  589. 	unsigned int	mpll_con0;
    590. 

  590. 	unsigned int	mpll_con1;
    591. 

  591. 	unsigned char	res16[0xf8];
    592. 

  592. 	unsigned int	src_core0;
    593. 

  593. 	unsigned int	src_core1;
    594. 

  594. 	unsigned char	res17[0xf8];
    595. 

  595. 	unsigned int	src_mask_core;
    596. 

  596. 	unsigned char	res18[0x100];
    597. 

  597. 	unsigned int	mux_stat_core1;
    598. 

  598. 	unsigned char	res19[0xf8];
    599. 

  599. 	unsigned int	div_core0;
    600. 

  600. 	unsigned int	div_core1;
    601. 

  601. 	unsigned int	div_sysrgt;
    602. 

  602. 	unsigned char	res20[0xf4];
    603. 

  603. 	unsigned int	div_stat_core0;
    604. 

  604. 	unsigned int	div_stat_core1;
    605. 

  605. 	unsigned int	div_stat_sysrgt;
    606. 

  606. 	unsigned char	res21[0x2f4];
    607. 

  607. 	unsigned int	gate_ip_core;
    608. 

  608. 	unsigned int	gate_ip_sysrgt;
    609. 

  609. 	unsigned char	res22[0x8];
    610. 

  610. 	unsigned int	c2c_monitor;
    611. 

  611. 	unsigned char	res23[0xec];
    612. 

  612. 	unsigned int	clkout_cmu_core;
    613. 

  613. 	unsigned int	clkout_cmu_core_div_stat;
    614. 

  614. 	unsigned char	res24[0x5f8];
    615. 

  615. 	unsigned int	dcgidx_map0;
    616. 

  616. 	unsigned int	dcgidx_map1;
    617. 

  617. 	unsigned int	dcgidx_map2;
    618. 

  618. 	unsigned char	res25[0x14];
    619. 

  619. 	unsigned int	dcgperf_map0;
    620. 

  620. 	unsigned int	dcgperf_map1;
    621. 

  621. 	unsigned char	res26[0x18];
    622. 

  622. 	unsigned int	dvcidx_map;
    623. 

  623. 	unsigned char	res27[0x1c];
    624. 

  624. 	unsigned int	freq_cpu;
    625. 

  625. 	unsigned int	freq_dpm;
    626. 

  626. 	unsigned char	res28[0x18];
    627. 

  627. 	unsigned int	dvsemclk_en;
    628. 

  628. 	unsigned int	maxperf;
    629. 

  629. 	unsigned char	res29[0xf78];
    630. 

  630. 	unsigned int	c2c_config;
    631. 

  631. 	unsigned char	res30[0x24fc];
    632. 

  632. 	unsigned int	div_acp;
    633. 

  633. 	unsigned char	res31[0xfc];
    634. 

  634. 	unsigned int	div_stat_acp;
    635. 

  635. 	unsigned char	res32[0x1fc];
    636. 

  636. 	unsigned int	gate_ip_acp;
    637. 

  637. 	unsigned char	res33[0xfc];
    638. 

  638. 	unsigned int	div_syslft;
    639. 

  639. 	unsigned char	res34[0xc];
    640. 

  640. 	unsigned int	div_stat_syslft;
    641. 

  641. 	unsigned char	res35[0x1c];
    642. 

  642. 	unsigned int	gate_ip_syslft;
    643. 

  643. 	unsigned char	res36[0xcc];
    644. 

  644. 	unsigned int	clkout_cmu_acp;
    645. 

  645. 	unsigned int	clkout_cmu_acp_div_stat;
    646. 

  646. 	unsigned char	res37[0x8];
    647. 

  647. 	unsigned int	ufmc_config;
    648. 

  648. 	unsigned char	res38[0x38ec];
    649. 

  649. 	unsigned int	div_isp0;
    650. 

  650. 	unsigned int	div_isp1;
    651. 

  651. 	unsigned int	div_isp2;
    652. 

  652. 	unsigned char	res39[0xf4];
    653. 

  653. 	unsigned int	div_stat_isp0;
    654. 

  654. 	unsigned int	div_stat_isp1;
    655. 

  655. 	unsigned int	div_stat_isp2;
    656. 

  656. 	unsigned char	res40[0x3f4];
    657. 

  657. 	unsigned int	gate_ip_isp0;
    658. 

  658. 	unsigned int	gate_ip_isp1;
    659. 

  659. 	unsigned char	res41[0xf8];
    660. 

  660. 	unsigned int	gate_sclk_isp;
    661. 

  661. 	unsigned char	res42[0xc];
    662. 

  662. 	unsigned int	mcuisp_pwr_ctrl;
    663. 

  663. 	unsigned char	res43[0xec];
    664. 

  664. 	unsigned int	clkout_cmu_isp;
    665. 

  665. 	unsigned int	clkout_cmu_isp_div_stat;
    666. 

  666. 	unsigned char	res44[0x3618];
    667. 

  667. 	unsigned int	cpll_lock;
    668. 

  668. 	unsigned char	res45[0xc];
    669. 

  669. 	unsigned int	epll_lock;
    670. 

  670. 	unsigned char	res46[0xc];
    671. 

  671. 	unsigned int	vpll_lock;
    672. 

  672. 	unsigned char	res47[0xc];
    673. 

  673. 	unsigned int	gpll_lock;
    674. 

  674. 	unsigned char	res48[0xcc];
    675. 

  675. 	unsigned int	cpll_con0;
    676. 

  676. 	unsigned int	cpll_con1;
    677. 

  677. 	unsigned char	res49[0x8];
    678. 

  678. 	unsigned int	epll_con0;
    679. 

  679. 	unsigned int	epll_con1;
    680. 

  680. 	unsigned int	epll_con2;
    681. 

  681. 	unsigned char	res50[0x4];
    682. 

  682. 	unsigned int	vpll_con0;
    683. 

  683. 	unsigned int	vpll_con1;
    684. 

  684. 	unsigned int	vpll_con2;
    685. 

  685. 	unsigned char	res51[0x4];
    686. 

  686. 	unsigned int	gpll_con0;
    687. 

  687. 	unsigned int	gpll_con1;
    688. 

  688. 	unsigned char	res52[0xb8];
    689. 

  689. 	unsigned int	src_top0;
    690. 

  690. 	unsigned int	src_top1;
    691. 

  691. 	unsigned int	src_top2;
    692. 

  692. 	unsigned int	src_top3;
    693. 

  693. 	unsigned int	src_gscl;
    694. 

  694. 	unsigned char	res53[0x8];
    695. 

  695. 	unsigned int	src_disp1_0;
    696. 

  696. 	unsigned char	res54[0x10];
    697. 

  697. 	unsigned int	src_mau;
    698. 

  698. 	unsigned int	src_fsys;
    699. 

  699. 	unsigned int	src_gen;
    700. 

  700. 	unsigned char	res55[0x4];
    701. 

  701. 	unsigned int	src_peric0;
    702. 

  702. 	unsigned int	src_peric1;
    703. 

  703. 	unsigned char	res56[0x18];
    704. 

  704. 	unsigned int	sclk_src_isp;
    705. 

  705. 	unsigned char	res57[0x9c];
    706. 

  706. 	unsigned int	src_mask_top;
    707. 

  707. 	unsigned char	res58[0xc];
    708. 

  708. 	unsigned int	src_mask_gscl;
    709. 

  709. 	unsigned char	res59[0x8];
    710. 

  710. 	unsigned int	src_mask_disp1_0;
    711. 

  711. 	unsigned char	res60[0x4];
    712. 

  712. 	unsigned int	src_mask_mau;
    713. 

  713. 	unsigned char	res61[0x8];
    714. 

  714. 	unsigned int	src_mask_fsys;
    715. 

  715. 	unsigned int	src_mask_gen;
    716. 

  716. 	unsigned char	res62[0x8];
    717. 

  717. 	unsigned int	src_mask_peric0;
    718. 

  718. 	unsigned int	src_mask_peric1;
    719. 

  719. 	unsigned char	res63[0x18];
    720. 

  720. 	unsigned int	src_mask_isp;
    721. 

  721. 	unsigned char	res67[0x9c];
    722. 

  722. 	unsigned int	mux_stat_top0;
    723. 

  723. 	unsigned int	mux_stat_top1;
    724. 

  724. 	unsigned int	mux_stat_top2;
    725. 

  725. 	unsigned int	mux_stat_top3;
    726. 

  726. 	unsigned char	res68[0xf0];
    727. 

  727. 	unsigned int	div_top0;
    728. 

  728. 	unsigned int	div_top1;
    729. 

  729. 	unsigned char	res69[0x8];
    730. 

  730. 	unsigned int	div_gscl;
    731. 

  731. 	unsigned char	res70[0x8];
    732. 

  732. 	unsigned int	div_disp1_0;
    733. 

  733. 	unsigned char	res71[0xc];
    734. 

  734. 	unsigned int	div_gen;
    735. 

  735. 	unsigned char	res72[0x4];
    736. 

  736. 	unsigned int	div_mau;
    737. 

  737. 	unsigned int	div_fsys0;
    738. 

  738. 	unsigned int	div_fsys1;
    739. 

  739. 	unsigned int	div_fsys2;
    740. 

  740. 	unsigned char	res73[0x4];
    741. 

  741. 	unsigned int	div_peric0;
    742. 

  742. 	unsigned int	div_peric1;
    743. 

  743. 	unsigned int	div_peric2;
    744. 

  744. 	unsigned int	div_peric3;
    745. 

  745. 	unsigned int	div_peric4;
    746. 

  746. 	unsigned int	div_peric5;
    747. 

  747. 	unsigned char	res74[0x10];
    748. 

  748. 	unsigned int	sclk_div_isp;
    749. 

  749. 	unsigned char	res75[0xc];
    750. 

  750. 	unsigned int	div2_ratio0;
    751. 

  751. 	unsigned int	div2_ratio1;
    752. 

  752. 	unsigned char	res76[0x8];
    753. 

  753. 	unsigned int	div4_ratio;
    754. 

  754. 	unsigned char	res77[0x6c];
    755. 

  755. 	unsigned int	div_stat_top0;
    756. 

  756. 	unsigned int	div_stat_top1;
    757. 

  757. 	unsigned char	res78[0x8];
    758. 

  758. 	unsigned int	div_stat_gscl;
    759. 

  759. 	unsigned char	res79[0x8];
    760. 

  760. 	unsigned int	div_stat_disp1_0;
    761. 

  761. 	unsigned char	res80[0xc];
    762. 

  762. 	unsigned int	div_stat_gen;
    763. 

  763. 	unsigned char	res81[0x4];
    764. 

  764. 	unsigned int	div_stat_mau;
    765. 

  765. 	unsigned int	div_stat_fsys0;
    766. 

  766. 	unsigned int	div_stat_fsys1;
    767. 

  767. 	unsigned int	div_stat_fsys2;
    768. 

  768. 	unsigned char	res82[0x4];
    769. 

  769. 	unsigned int	div_stat_peric0;
    770. 

  770. 	unsigned int	div_stat_peric1;
    771. 

  771. 	unsigned int	div_stat_peric2;
    772. 

  772. 	unsigned int	div_stat_peric3;
    773. 

  773. 	unsigned int	div_stat_peric4;
    774. 

  774. 	unsigned int	div_stat_peric5;
    775. 

  775. 	unsigned char	res83[0x10];
    776. 

  776. 	unsigned int	sclk_div_stat_isp;
    777. 

  777. 	unsigned char	res84[0xc];
    778. 

  778. 	unsigned int	div2_stat0;
    779. 

  779. 	unsigned int	div2_stat1;
    780. 

  780. 	unsigned char	res85[0x8];
    781. 

  781. 	unsigned int	div4_stat;
    782. 

  782. 	unsigned char	res86[0x184];
    783. 

  783. 	unsigned int	gate_top_sclk_disp1;
    784. 

  784. 	unsigned int	gate_top_sclk_gen;
    785. 

  785. 	unsigned char	res87[0xc];
    786. 

  786. 	unsigned int	gate_top_sclk_mau;
    787. 

  787. 	unsigned int	gate_top_sclk_fsys;
    788. 

  788. 	unsigned char	res88[0xc];
    789. 

  789. 	unsigned int	gate_top_sclk_peric;
    790. 

  790. 	unsigned char	res89[0x1c];
    791. 

  791. 	unsigned int	gate_top_sclk_isp;
    792. 

  792. 	unsigned char	res90[0xac];
    793. 

  793. 	unsigned int	gate_ip_gscl;
    794. 

  794. 	unsigned char	res91[0x4];
    795. 

  795. 	unsigned int	gate_ip_disp1;
    796. 

  796. 	unsigned int	gate_ip_mfc;
    797. 

  797. 	unsigned int	gate_ip_g3d;
    798. 

  798. 	unsigned int	gate_ip_gen;
    799. 

  799. 	unsigned char	res92[0xc];
    800. 

  800. 	unsigned int	gate_ip_fsys;
    801. 

  801. 	unsigned char	res93[0x8];
    802. 

  802. 	unsigned int	gate_ip_peric;
    803. 

  803. 	unsigned char	res94[0xc];
    804. 

  804. 	unsigned int	gate_ip_peris;
    805. 

  805. 	unsigned char	res95[0x1c];
    806. 

  806. 	unsigned int	gate_block;
    807. 

  807. 	unsigned char	res96[0x1c];
    808. 

  808. 	unsigned int	mcuiop_pwr_ctrl;
    809. 

  809. 	unsigned char	res97[0x5c];
    810. 

  810. 	unsigned int	clkout_cmu_top;
    811. 

  811. 	unsigned int	clkout_cmu_top_div_stat;
    812. 

  812. 	unsigned char	res98[0x37f8];
    813. 

  813. 	unsigned int	src_lex;
    814. 

  814. 	unsigned char	res99[0x1fc];
    815. 

  815. 	unsigned int	mux_stat_lex;
    816. 

  816. 	unsigned char	res100[0xfc];
    817. 

  817. 	unsigned int	div_lex;
    818. 

  818. 	unsigned char	res101[0xfc];
    819. 

  819. 	unsigned int	div_stat_lex;
    820. 

  820. 	unsigned char	res102[0x1fc];
    821. 

  821. 	unsigned int	gate_ip_lex;
    822. 

  822. 	unsigned char	res103[0x1fc];
    823. 

  823. 	unsigned int	clkout_cmu_lex;
    824. 

  824. 	unsigned int	clkout_cmu_lex_div_stat;
    825. 

  825. 	unsigned char	res104[0x3af8];
    826. 

  826. 	unsigned int	div_r0x;
    827. 

  827. 	unsigned char	res105[0xfc];
    828. 

  828. 	unsigned int	div_stat_r0x;
    829. 

  829. 	unsigned char	res106[0x1fc];
    830. 

  830. 	unsigned int	gate_ip_r0x;
    831. 

  831. 	unsigned char	res107[0x1fc];
    832. 

  832. 	unsigned int	clkout_cmu_r0x;
    833. 

  833. 	unsigned int	clkout_cmu_r0x_div_stat;
    834. 

  834. 	unsigned char	res108[0x3af8];
    835. 

  835. 	unsigned int	div_r1x;
    836. 

  836. 	unsigned char	res109[0xfc];
    837. 

  837. 	unsigned int	div_stat_r1x;
    838. 

  838. 	unsigned char	res110[0x1fc];
    839. 

  839. 	unsigned int	gate_ip_r1x;
    840. 

  840. 	unsigned char	res111[0x1fc];
    841. 

  841. 	unsigned int	clkout_cmu_r1x;
    842. 

  842. 	unsigned int	clkout_cmu_r1x_div_stat;
    843. 

  843. 	unsigned char	res112[0x3608];
    844. 

  844. 	unsigned int	bpll_lock;
    845. 

  845. 	unsigned char	res113[0xfc];
    846. 

  846. 	unsigned int	bpll_con0;
    847. 

  847. 	unsigned int	bpll_con1;
    848. 

  848. 	unsigned char	res114[0xe8];
    849. 

  849. 	unsigned int	src_cdrex;
    850. 

  850. 	unsigned char	res115[0x1fc];
    851. 

  851. 	unsigned int	mux_stat_cdrex;
    852. 

  852. 	unsigned char	res116[0xfc];
    853. 

  853. 	unsigned int	div_cdrex;
    854. 

  854. 	unsigned char	res117[0xfc];
    855. 

  855. 	unsigned int	div_stat_cdrex;
    856. 

  856. 	unsigned char	res118[0x2fc];
    857. 

  857. 	unsigned int	gate_ip_cdrex;
    858. 

  858. 	unsigned char	res119[0x10];
    859. 

  859. 	unsigned int	dmc_freq_ctrl;
    860. 

  860. 	unsigned char	res120[0x4];
    861. 

  861. 	unsigned int	drex2_pause;
    862. 

  862. 	unsigned char	res121[0xe0];
    863. 

  863. 	unsigned int	clkout_cmu_cdrex;
    864. 

  864. 	unsigned int	clkout_cmu_cdrex_div_stat;
    865. 

  865. 	unsigned char	res122[0x8];
    866. 

  866. 	unsigned int	lpddr3phy_ctrl;
    867. 

  867. 	unsigned int	lpddr3phy_con0;
    868. 

  868. 	unsigned int	lpddr3phy_con1;
    869. 

  869. 	unsigned int	lpddr3phy_con2;
    870. 

  870. 	unsigned int	lpddr3phy_con3;
    871. 

  871. 	unsigned int	pll_div2_sel;
    872. 

  872. 	unsigned char	res123[0xf5d8];
    873. 

  873. };
    874. 

  874. 

  875. /* structure for epll configuration used in audio clock configuration */
    876. 

  876. struct set_epll_con_val {
    877. 

  877. 	unsigned int freq_out;		/* frequency out */
    878. 

  878. 	unsigned int en_lock_det;	/* enable lock detect */
    879. 

  879. 	unsigned int m_div;		/* m divider value */
    880. 

  880. 	unsigned int p_div;		/* p divider value */
    881. 

  881. 	unsigned int s_div;		/* s divider value */
    882. 

  882. 	unsigned int k_dsm;		/* k value of delta signal modulator */
    883. 

  883. };
    884. 

  884. #endif
    885. 

  885. 

  886. #define MPLL_FOUT_SEL_SHIFT	4
    887. 

  887. #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
    888. 

  888. #define TIMEOUT_EPLL_LOCK		1000
    889. 

  889. 

  890. #define AUDIO_0_RATIO_MASK		0x0f
    891. 

  891. #define AUDIO_1_RATIO_MASK		0x0f
    892. 

  892. 

  893. #define AUDIO1_SEL_MASK			0xf
    894. 

  894. #define CLK_SRC_SCLK_EPLL		0x7
    895. 

  895. 

  896. /* CON0 bit-fields */
    897. 

  897. #define EPLL_CON0_MDIV_MASK		0x1ff
    898. 

  898. #define EPLL_CON0_PDIV_MASK		0x3f
    899. 

  899. #define EPLL_CON0_SDIV_MASK		0x7
    900. 

  900. #define EPLL_CON0_MDIV_SHIFT		16
    901. 

  901. #define EPLL_CON0_PDIV_SHIFT		8
    902. 

  902. #define EPLL_CON0_SDIV_SHIFT		0
    903. 

  903. #define EPLL_CON0_LOCK_DET_EN_SHIFT	28
    904. 

  904. #define EPLL_CON0_LOCK_DET_EN_MASK	1
    905. 

  905. 

  906. #define MPLL_FOUT_SEL_MASK	0x1
    907. 

  907. #define BPLL_FOUT_SEL_SHIFT	0
    908. 

  908. #define BPLL_FOUT_SEL_MASK	0x1
    909. 

  909. #endif
    910.