serial_smc.c 13 KB

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  1. /*
  2. * (C) Copyright 2000, 2001, 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
  24. * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
  25. * Linux/PPC sources (m8260_tty.c had no copyright info in it).
  26. */
  27. /*
  28. * Minimal serial functions needed to use one of the SMC ports
  29. * as serial console interface.
  30. */
  31. #include <common.h>
  32. #include <mpc8260.h>
  33. #include <asm/cpm_8260.h>
  34. #include <serial.h>
  35. #include <linux/compiler.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #if defined(CONFIG_CONS_ON_SMC)
  38. #if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */
  39. #define SMC_INDEX 0
  40. #define PROFF_SMC_BASE PROFF_SMC1_BASE
  41. #define PROFF_SMC PROFF_SMC1
  42. #define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
  43. #define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
  44. #define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
  45. #define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
  46. #elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */
  47. #define SMC_INDEX 1
  48. #define PROFF_SMC_BASE PROFF_SMC2_BASE
  49. #define PROFF_SMC PROFF_SMC2
  50. #define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
  51. #define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
  52. #define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
  53. #define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
  54. #else
  55. #error "console not correctly defined"
  56. #endif
  57. #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
  58. #define CONFIG_SYS_SMC_RXBUFLEN 1
  59. #define CONFIG_SYS_MAXIDLE 0
  60. #else
  61. #if !defined(CONFIG_SYS_MAXIDLE)
  62. #error "you must define CONFIG_SYS_MAXIDLE"
  63. #endif
  64. #endif
  65. typedef volatile struct serialbuffer {
  66. cbd_t rxbd; /* Rx BD */
  67. cbd_t txbd; /* Tx BD */
  68. uint rxindex; /* index for next character to read */
  69. volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
  70. volatile uchar txbuf; /* tx buffers */
  71. } serialbuffer_t;
  72. /* map rs_table index to baud rate generator index */
  73. static unsigned char brg_map[] = {
  74. 6, /* BRG7 for SMC1 */
  75. 7, /* BRG8 for SMC2 */
  76. 0, /* BRG1 for SCC1 */
  77. 1, /* BRG1 for SCC2 */
  78. 2, /* BRG1 for SCC3 */
  79. 3, /* BRG1 for SCC4 */
  80. };
  81. static int mpc8260_smc_serial_init(void)
  82. {
  83. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  84. volatile smc_t *sp;
  85. volatile smc_uart_t *up;
  86. volatile cpm8260_t *cp = &(im->im_cpm);
  87. uint dpaddr;
  88. volatile serialbuffer_t *rtx;
  89. /* initialize pointers to SMC */
  90. sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
  91. *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
  92. up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
  93. /* Disable transmitter/receiver. */
  94. sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  95. /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
  96. /* Allocate space for two buffer descriptors in the DP ram.
  97. * damm: allocating space after the two buffers for rx/tx data
  98. */
  99. /* allocate size of struct serialbuffer with bd rx/tx,
  100. * buffer rx/tx and rx index
  101. */
  102. dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
  103. rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
  104. /* Set the physical address of the host memory buffers in
  105. * the buffer descriptors.
  106. */
  107. rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
  108. rtx->rxbd.cbd_sc = 0;
  109. rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
  110. rtx->txbd.cbd_sc = 0;
  111. /* Set up the uart parameters in the parameter ram. */
  112. up->smc_rbase = dpaddr;
  113. up->smc_tbase = dpaddr+sizeof(cbd_t);
  114. up->smc_rfcr = CPMFCR_EB;
  115. up->smc_tfcr = CPMFCR_EB;
  116. up->smc_brklen = 0;
  117. up->smc_brkec = 0;
  118. up->smc_brkcr = 0;
  119. /* Set UART mode, 8 bit, no parity, one stop.
  120. * Enable receive and transmit.
  121. */
  122. sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
  123. /* Mask all interrupts and remove anything pending. */
  124. sp->smc_smcm = 0;
  125. sp->smc_smce = 0xff;
  126. /* put the SMC channel into NMSI (non multiplexd serial interface)
  127. * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
  128. */
  129. im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
  130. /* Set up the baud rate generator. */
  131. serial_setbrg ();
  132. /* Make the first buffer the only buffer. */
  133. rtx->txbd.cbd_sc |= BD_SC_WRAP;
  134. rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
  135. /* single/multi character receive. */
  136. up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
  137. up->smc_maxidl = CONFIG_SYS_MAXIDLE;
  138. rtx->rxindex = 0;
  139. /* Initialize Tx/Rx parameters. */
  140. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  141. ;
  142. cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
  143. 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  144. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  145. ;
  146. /* Enable transmitter/receiver. */
  147. sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
  148. return (0);
  149. }
  150. static void mpc8260_smc_serial_setbrg(void)
  151. {
  152. #if defined(CONFIG_CONS_USE_EXTC)
  153. m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
  154. CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
  155. #else
  156. m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
  157. #endif
  158. }
  159. static void mpc8260_smc_serial_putc(const char c)
  160. {
  161. volatile smc_uart_t *up;
  162. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  163. volatile serialbuffer_t *rtx;
  164. if (c == '\n')
  165. serial_putc ('\r');
  166. up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
  167. rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
  168. /* Wait for last character to go. */
  169. while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
  170. ;
  171. rtx->txbuf = c;
  172. rtx->txbd.cbd_datlen = 1;
  173. rtx->txbd.cbd_sc |= BD_SC_READY;
  174. }
  175. static void mpc8260_smc_serial_puts(const char *s)
  176. {
  177. while (*s) {
  178. serial_putc (*s++);
  179. }
  180. }
  181. static int mpc8260_smc_serial_getc(void)
  182. {
  183. volatile smc_uart_t *up;
  184. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  185. volatile serialbuffer_t *rtx;
  186. unsigned char c;
  187. up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
  188. rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
  189. /* Wait for character to show up. */
  190. while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
  191. ;
  192. /* the characters are read one by one,
  193. * use the rxindex to know the next char to deliver
  194. */
  195. c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
  196. rtx->rxindex++;
  197. /* check if all char are readout, then make prepare for next receive */
  198. if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
  199. rtx->rxindex = 0;
  200. rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
  201. }
  202. return(c);
  203. }
  204. static int mpc8260_smc_serial_tstc(void)
  205. {
  206. volatile smc_uart_t *up;
  207. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  208. volatile serialbuffer_t *rtx;
  209. up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
  210. rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
  211. return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
  212. }
  213. #ifdef CONFIG_SERIAL_MULTI
  214. static struct serial_device mpc8260_smc_serial_drv = {
  215. .name = "mpc8260_smc_uart",
  216. .start = mpc8260_smc_serial_init,
  217. .stop = NULL,
  218. .setbrg = mpc8260_smc_serial_setbrg,
  219. .putc = mpc8260_smc_serial_putc,
  220. .puts = mpc8260_smc_serial_puts,
  221. .getc = mpc8260_smc_serial_getc,
  222. .tstc = mpc8260_smc_serial_tstc,
  223. };
  224. void mpc8260_smc_serial_initialize(void)
  225. {
  226. serial_register(&mpc8260_smc_serial_drv);
  227. }
  228. __weak struct serial_device *default_serial_console(void)
  229. {
  230. return &mpc8260_smc_serial_drv;
  231. }
  232. #else
  233. int serial_init(void)
  234. {
  235. return mpc8260_smc_serial_init();
  236. }
  237. void serial_setbrg(void)
  238. {
  239. mpc8260_smc_serial_setbrg();
  240. }
  241. void serial_putc(const char c)
  242. {
  243. mpc8260_smc_serial_putc(c);
  244. }
  245. void serial_puts(const char *s)
  246. {
  247. mpc8260_smc_serial_puts(s);
  248. }
  249. int serial_getc(void)
  250. {
  251. return mpc8260_smc_serial_getc();
  252. }
  253. int serial_tstc(void)
  254. {
  255. return mpc8260_smc_serial_tstc();
  256. }
  257. #endif
  258. #endif /* CONFIG_CONS_ON_SMC */
  259. #if defined(CONFIG_KGDB_ON_SMC)
  260. #if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
  261. #error Whoops! serial console and kgdb are on the same smc serial port
  262. #endif
  263. #if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */
  264. #define KGDB_SMC_INDEX 0
  265. #define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE
  266. #define KGDB_PROFF_SMC PROFF_SMC1
  267. #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
  268. #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
  269. #define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
  270. #define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
  271. #elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */
  272. #define KGDB_SMC_INDEX 1
  273. #define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE
  274. #define KGDB_PROFF_SMC PROFF_SMC2
  275. #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
  276. #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
  277. #define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
  278. #define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
  279. #else
  280. #error "console not correctly defined"
  281. #endif
  282. void
  283. kgdb_serial_init (void)
  284. {
  285. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  286. volatile smc_t *sp;
  287. volatile smc_uart_t *up;
  288. volatile cbd_t *tbdf, *rbdf;
  289. volatile cpm8260_t *cp = &(im->im_cpm);
  290. uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
  291. char *s, *e;
  292. if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
  293. ulong rate = simple_strtoul(s, &e, 10);
  294. if (e > s && *e == '\0')
  295. speed = rate;
  296. }
  297. /* initialize pointers to SMC */
  298. sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
  299. *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
  300. up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
  301. /* Disable transmitter/receiver. */
  302. sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  303. /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
  304. /* Allocate space for two buffer descriptors in the DP ram.
  305. * damm: allocating space after the two buffers for rx/tx data
  306. */
  307. dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
  308. /* Set the physical address of the host memory buffers in
  309. * the buffer descriptors.
  310. */
  311. rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
  312. rbdf->cbd_bufaddr = (uint) (rbdf+2);
  313. rbdf->cbd_sc = 0;
  314. tbdf = rbdf + 1;
  315. tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
  316. tbdf->cbd_sc = 0;
  317. /* Set up the uart parameters in the parameter ram. */
  318. up->smc_rbase = dpaddr;
  319. up->smc_tbase = dpaddr+sizeof(cbd_t);
  320. up->smc_rfcr = CPMFCR_EB;
  321. up->smc_tfcr = CPMFCR_EB;
  322. up->smc_brklen = 0;
  323. up->smc_brkec = 0;
  324. up->smc_brkcr = 0;
  325. /* Set UART mode, 8 bit, no parity, one stop.
  326. * Enable receive and transmit.
  327. */
  328. sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
  329. /* Mask all interrupts and remove anything pending. */
  330. sp->smc_smcm = 0;
  331. sp->smc_smce = 0xff;
  332. /* put the SMC channel into NMSI (non multiplexd serial interface)
  333. * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
  334. */
  335. im->im_cpmux.cmx_smr =
  336. (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
  337. /* Set up the baud rate generator. */
  338. #if defined(CONFIG_KGDB_USE_EXTC)
  339. m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
  340. CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
  341. #else
  342. m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
  343. #endif
  344. /* Make the first buffer the only buffer. */
  345. tbdf->cbd_sc |= BD_SC_WRAP;
  346. rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
  347. /* Single character receive. */
  348. up->smc_mrblr = 1;
  349. up->smc_maxidl = 0;
  350. /* Initialize Tx/Rx parameters. */
  351. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  352. ;
  353. cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
  354. 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  355. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  356. ;
  357. /* Enable transmitter/receiver. */
  358. sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
  359. printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
  360. }
  361. void
  362. putDebugChar(const char c)
  363. {
  364. volatile cbd_t *tbdf;
  365. volatile char *buf;
  366. volatile smc_uart_t *up;
  367. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  368. if (c == '\n')
  369. putDebugChar ('\r');
  370. up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
  371. tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
  372. /* Wait for last character to go. */
  373. buf = (char *)tbdf->cbd_bufaddr;
  374. while (tbdf->cbd_sc & BD_SC_READY)
  375. ;
  376. *buf = c;
  377. tbdf->cbd_datlen = 1;
  378. tbdf->cbd_sc |= BD_SC_READY;
  379. }
  380. void
  381. putDebugStr (const char *s)
  382. {
  383. while (*s) {
  384. putDebugChar (*s++);
  385. }
  386. }
  387. int
  388. getDebugChar(void)
  389. {
  390. volatile cbd_t *rbdf;
  391. volatile unsigned char *buf;
  392. volatile smc_uart_t *up;
  393. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  394. unsigned char c;
  395. up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
  396. rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
  397. /* Wait for character to show up. */
  398. buf = (unsigned char *)rbdf->cbd_bufaddr;
  399. while (rbdf->cbd_sc & BD_SC_EMPTY)
  400. ;
  401. c = *buf;
  402. rbdf->cbd_sc |= BD_SC_EMPTY;
  403. return(c);
  404. }
  405. void
  406. kgdb_interruptible(int yes)
  407. {
  408. return;
  409. }
  410. #endif /* CONFIG_KGDB_ON_SMC */