da850evm.c 5.7 KB

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  1. /*
  2. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * Based on da830evm.c. Original Copyrights follow:
  5. *
  6. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <common.h>
  24. #include <i2c.h>
  25. #include <net.h>
  26. #include <netdev.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/emif_defs.h>
  29. #include <asm/arch/emac_defs.h>
  30. #include <asm/io.h>
  31. #include "../common/misc.h"
  32. #include "common.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  35. /* SPI0 pin muxer settings */
  36. static const struct pinmux_config spi1_pins[] = {
  37. { pinmux(5), 1, 1 },
  38. { pinmux(5), 1, 2 },
  39. { pinmux(5), 1, 4 },
  40. { pinmux(5), 1, 5 }
  41. };
  42. /* UART pin muxer settings */
  43. static const struct pinmux_config uart_pins[] = {
  44. { pinmux(0), 4, 6 },
  45. { pinmux(0), 4, 7 },
  46. { pinmux(4), 2, 4 },
  47. { pinmux(4), 2, 5 }
  48. };
  49. #ifdef CONFIG_DRIVER_TI_EMAC
  50. static const struct pinmux_config emac_pins[] = {
  51. { pinmux(2), 8, 1 },
  52. { pinmux(2), 8, 2 },
  53. { pinmux(2), 8, 3 },
  54. { pinmux(2), 8, 4 },
  55. { pinmux(2), 8, 5 },
  56. { pinmux(2), 8, 6 },
  57. { pinmux(2), 8, 7 },
  58. { pinmux(3), 8, 0 },
  59. { pinmux(3), 8, 1 },
  60. { pinmux(3), 8, 2 },
  61. { pinmux(3), 8, 3 },
  62. { pinmux(3), 8, 4 },
  63. { pinmux(3), 8, 5 },
  64. { pinmux(3), 8, 6 },
  65. { pinmux(3), 8, 7 },
  66. { pinmux(4), 8, 0 },
  67. { pinmux(4), 8, 1 }
  68. };
  69. #endif /* CONFIG_DRIVER_TI_EMAC */
  70. /* I2C pin muxer settings */
  71. static const struct pinmux_config i2c_pins[] = {
  72. { pinmux(4), 2, 2 },
  73. { pinmux(4), 2, 3 }
  74. };
  75. #ifdef CONFIG_NAND_DAVINCI
  76. const struct pinmux_config nand_pins[] = {
  77. { pinmux(7), 1, 1 },
  78. { pinmux(7), 1, 2 },
  79. { pinmux(7), 1, 4 },
  80. { pinmux(7), 1, 5 },
  81. { pinmux(9), 1, 0 },
  82. { pinmux(9), 1, 1 },
  83. { pinmux(9), 1, 2 },
  84. { pinmux(9), 1, 3 },
  85. { pinmux(9), 1, 4 },
  86. { pinmux(9), 1, 5 },
  87. { pinmux(9), 1, 6 },
  88. { pinmux(9), 1, 7 },
  89. { pinmux(12), 1, 5 },
  90. { pinmux(12), 1, 6 }
  91. };
  92. #endif
  93. static const struct pinmux_resource pinmuxes[] = {
  94. #ifdef CONFIG_SPI_FLASH
  95. PINMUX_ITEM(spi1_pins),
  96. #endif
  97. PINMUX_ITEM(uart_pins),
  98. PINMUX_ITEM(i2c_pins),
  99. #ifdef CONFIG_NAND_DAVINCI
  100. PINMUX_ITEM(nand_pins),
  101. #endif
  102. };
  103. static const struct lpsc_resource lpsc[] = {
  104. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  105. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  106. { DAVINCI_LPSC_EMAC }, /* image download */
  107. { DAVINCI_LPSC_UART2 }, /* console */
  108. { DAVINCI_LPSC_GPIO },
  109. };
  110. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  111. #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
  112. #endif
  113. /*
  114. * get_board_rev() - setup to pass kernel board revision information
  115. * Returns:
  116. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  117. * 0000b - 300 MHz
  118. * 0001b - 372 MHz
  119. * 0010b - 408 MHz
  120. * 0011b - 456 MHz
  121. */
  122. u32 get_board_rev(void)
  123. {
  124. char *s;
  125. u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
  126. u32 rev = 0;
  127. s = getenv("maxcpuclk");
  128. if (s)
  129. maxcpuclk = simple_strtoul(s, NULL, 10);
  130. if (maxcpuclk >= 456000000)
  131. rev = 3;
  132. else if (maxcpuclk >= 408000000)
  133. rev = 2;
  134. else if (maxcpuclk >= 372000000)
  135. rev = 1;
  136. return rev;
  137. }
  138. int board_init(void)
  139. {
  140. #ifndef CONFIG_USE_IRQ
  141. irq_init();
  142. #endif
  143. #ifdef CONFIG_NAND_DAVINCI
  144. /*
  145. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  146. * Linux kernel @ 25MHz EMIFA
  147. */
  148. writel((DAVINCI_ABCR_WSETUP(0) |
  149. DAVINCI_ABCR_WSTROBE(0) |
  150. DAVINCI_ABCR_WHOLD(0) |
  151. DAVINCI_ABCR_RSETUP(0) |
  152. DAVINCI_ABCR_RSTROBE(1) |
  153. DAVINCI_ABCR_RHOLD(0) |
  154. DAVINCI_ABCR_TA(0) |
  155. DAVINCI_ABCR_ASIZE_8BIT),
  156. &davinci_emif_regs->ab2cr); /* CS3 */
  157. #endif
  158. /* arch number of the board */
  159. gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
  160. /* address of boot parameters */
  161. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  162. /*
  163. * Power on required peripherals
  164. * ARM does not have access by default to PSC0 and PSC1
  165. * assuming here that the DSP bootloader has set the IOPU
  166. * such that PSC access is available to ARM
  167. */
  168. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  169. return 1;
  170. /* setup the SUSPSRC for ARM to control emulation suspend */
  171. writel(readl(&davinci_syscfg_regs->suspsrc) &
  172. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  173. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  174. DAVINCI_SYSCFG_SUSPSRC_UART2),
  175. &davinci_syscfg_regs->suspsrc);
  176. /* configure pinmux settings */
  177. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  178. return 1;
  179. #ifdef CONFIG_DRIVER_TI_EMAC
  180. if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
  181. return 1;
  182. /* set cfgchip3 to select MII */
  183. writel(readl(&davinci_syscfg_regs->cfgchip3) & ~(1 << 8),
  184. &davinci_syscfg_regs->cfgchip3);
  185. #endif /* CONFIG_DRIVER_TI_EMAC */
  186. /* enable the console UART */
  187. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  188. DAVINCI_UART_PWREMU_MGMT_UTRST),
  189. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  190. return 0;
  191. }
  192. #ifdef CONFIG_DRIVER_TI_EMAC
  193. /*
  194. * Initializes on-board ethernet controllers.
  195. */
  196. int board_eth_init(bd_t *bis)
  197. {
  198. if (!davinci_emac_initialize()) {
  199. printf("Error: Ethernet init failed!\n");
  200. return -1;
  201. }
  202. return 0;
  203. }
  204. #endif /* CONFIG_DRIVER_TI_EMAC */