sbc8560.h 15 KB

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  1. /*
  2. * (C) Copyright 2002,2003 Motorola,Inc.
  3. * Xianghua Xiao <X.Xiao@motorola.com>
  4. *
  5. * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
  6. * Added support for Wind River SBC8560 board
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * sbc8560 board configuration file.
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. /*
  32. * Top level Makefile configuration choices
  33. */
  34. #ifdef CONFIG_66
  35. #define CONFIG_PCI_66
  36. #endif
  37. /*
  38. * High Level Configuration Options
  39. */
  40. #define CONFIG_BOOKE 1 /* BOOKE */
  41. #define CONFIG_E500 1 /* BOOKE e500 family */
  42. #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
  43. #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
  44. #define CONFIG_SYS_TEXT_BASE 0xfffc0000
  45. #define CONFIG_CPM2 1 /* has CPM2 */
  46. #define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
  47. #define CONFIG_MPC8560 1
  48. /* XXX flagging this as something I might want to delete */
  49. #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
  50. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  51. #undef CONFIG_PCI /* pci ethernet support */
  52. #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  53. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  54. #define CONFIG_ENV_OVERWRITE
  55. /* Using Localbus SDRAM to emulate flash before we can program the flash,
  56. * normally you need a flash-boot image(u-boot.bin), if so undef this.
  57. */
  58. #undef CONFIG_RAM_AS_FLASH
  59. #if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
  60. #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
  61. #else
  62. #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
  63. #endif
  64. /* below can be toggled for performance analysis. otherwise use default */
  65. #define CONFIG_L2_CACHE /* toggle L2 cache */
  66. #undef CONFIG_BTB /* toggle branch predition */
  67. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  68. #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
  69. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  70. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  71. #define CONFIG_SYS_MEMTEST_END 0x00400000
  72. #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
  73. defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
  74. defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
  75. #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
  76. #endif
  77. #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
  78. /* DDR Setup */
  79. #define CONFIG_FSL_DDR1
  80. #undef CONFIG_FSL_DDR_INTERACTIVE
  81. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  82. #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  83. #undef CONFIG_DDR_SPD
  84. #if defined(CONFIG_MPC85xx_REV1)
  85. #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
  86. #endif
  87. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  88. #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  89. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  90. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  91. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  92. #define CONFIG_VERY_BIG_RAM
  93. #define CONFIG_NUM_DDR_CONTROLLERS 1
  94. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  95. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  96. /* I2C addresses of SPD EEPROMs */
  97. #define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
  98. #undef CONFIG_CLOCKS_IN_MHZ
  99. #if defined(CONFIG_RAM_AS_FLASH)
  100. #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
  101. #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
  102. #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
  103. #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
  104. #else /* Boot from real Flash */
  105. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
  106. #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
  107. #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
  108. #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
  109. #endif
  110. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  111. /* local bus definitions */
  112. #define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
  113. #define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
  114. #define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
  115. #define CONFIG_SYS_OR2_PRELIM 0x00000000
  116. #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
  117. #define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
  118. #if defined(CONFIG_RAM_AS_FLASH)
  119. #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
  120. #else
  121. #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
  122. #endif
  123. #define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
  124. #define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
  125. #if 1
  126. #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
  127. #else
  128. #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
  129. #endif
  130. #define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
  131. #define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
  132. #define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
  133. #define CONFIG_SYS_LBC_LBCR 0x00000000
  134. #define CONFIG_SYS_LBC_LSRT 0x20000000
  135. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  136. #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
  137. #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
  138. #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
  139. #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
  140. #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
  141. /* just hijack the MOT BCSR def for SBC8560 misc devices */
  142. #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
  143. /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
  144. #define CONFIG_SYS_INIT_RAM_LOCK 1
  145. #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
  146. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  147. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  148. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  149. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  150. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  151. /* Serial Port */
  152. #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
  153. #undef CONFIG_CONS_NONE /* define if console on something else */
  154. #define CONFIG_CONS_INDEX 1
  155. #define CONFIG_SYS_NS16550
  156. #define CONFIG_SYS_NS16550_SERIAL
  157. #define CONFIG_SYS_NS16550_REG_SIZE 1
  158. #define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
  159. #define CONFIG_BAUDRATE 9600
  160. #define CONFIG_SYS_BAUDRATE_TABLE \
  161. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  162. #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
  163. #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
  164. /* Use the HUSH parser */
  165. #define CONFIG_SYS_HUSH_PARSER
  166. #ifdef CONFIG_SYS_HUSH_PARSER
  167. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  168. #endif
  169. /* pass open firmware flat tree */
  170. #define CONFIG_OF_LIBFDT 1
  171. #define CONFIG_OF_BOARD_SETUP 1
  172. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  173. /*
  174. * I2C
  175. */
  176. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  177. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  178. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  179. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  180. #define CONFIG_SYS_I2C_SLAVE 0x7F
  181. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  182. #define CONFIG_SYS_I2C_OFFSET 0x3000
  183. #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
  184. #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
  185. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  186. #ifdef CONFIG_TSEC_ENET
  187. #ifndef CONFIG_MII
  188. #define CONFIG_MII 1 /* MII PHY management */
  189. #endif
  190. #define CONFIG_TSEC1 1
  191. #define CONFIG_TSEC1_NAME "TSEC0"
  192. #define CONFIG_TSEC2 1
  193. #define CONFIG_TSEC2_NAME "TSEC1"
  194. #define TSEC1_PHY_ADDR 0x19
  195. #define TSEC2_PHY_ADDR 0x1a
  196. #define TSEC1_PHYIDX 0
  197. #define TSEC2_PHYIDX 0
  198. #define TSEC1_FLAGS TSEC_GIGABIT
  199. #define TSEC2_FLAGS TSEC_GIGABIT
  200. /* Options are: TSEC[0-1] */
  201. #define CONFIG_ETHPRIME "TSEC0"
  202. #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
  203. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  204. #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
  205. #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  206. #if (CONFIG_ETHER_INDEX == 2)
  207. /*
  208. * - Rx-CLK is CLK13
  209. * - Tx-CLK is CLK14
  210. * - Select bus for bd/buffers
  211. * - Full duplex
  212. */
  213. #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  214. #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  215. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  216. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
  217. #elif (CONFIG_ETHER_INDEX == 3)
  218. /* need more definitions here for FE3 */
  219. #endif /* CONFIG_ETHER_INDEX */
  220. #define CONFIG_MII /* MII PHY management */
  221. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  222. /*
  223. * GPIO pins used for bit-banged MII communications
  224. */
  225. #define MDIO_PORT 2 /* Port C */
  226. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  227. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  228. #define MDC_DECLARE MDIO_DECLARE
  229. #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
  230. #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
  231. #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
  232. #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
  233. else iop->pdat &= ~0x00400000
  234. #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
  235. else iop->pdat &= ~0x00200000
  236. #define MIIDELAY udelay(1)
  237. #endif
  238. /*-----------------------------------------------------------------------
  239. * FLASH and environment organization
  240. */
  241. #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
  242. #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
  243. #if 0
  244. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  245. #define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
  246. #endif
  247. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
  248. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  249. #undef CONFIG_SYS_FLASH_CHECKSUM
  250. #define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
  251. #define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
  252. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  253. #if 0
  254. /* XXX This doesn't work and I don't want to fix it */
  255. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  256. #define CONFIG_SYS_RAMBOOT
  257. #else
  258. #undef CONFIG_SYS_RAMBOOT
  259. #endif
  260. #endif
  261. /* Environment */
  262. #if !defined(CONFIG_SYS_RAMBOOT)
  263. #if defined(CONFIG_RAM_AS_FLASH)
  264. #define CONFIG_ENV_IS_NOWHERE
  265. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
  266. #define CONFIG_ENV_SIZE 0x2000
  267. #else
  268. #define CONFIG_ENV_IS_IN_FLASH 1
  269. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  270. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  271. #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
  272. #endif
  273. #else
  274. #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
  275. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  276. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  277. #define CONFIG_ENV_SIZE 0x2000
  278. #endif
  279. #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
  280. /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
  281. #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
  282. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  283. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  284. /*
  285. * BOOTP options
  286. */
  287. #define CONFIG_BOOTP_BOOTFILESIZE
  288. #define CONFIG_BOOTP_BOOTPATH
  289. #define CONFIG_BOOTP_GATEWAY
  290. #define CONFIG_BOOTP_HOSTNAME
  291. /*
  292. * Command line configuration.
  293. */
  294. #include <config_cmd_default.h>
  295. #define CONFIG_CMD_PING
  296. #define CONFIG_CMD_I2C
  297. #define CONFIG_CMD_REGINFO
  298. #if defined(CONFIG_PCI)
  299. #define CONFIG_CMD_PCI
  300. #endif
  301. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  302. #define CONFIG_CMD_MII
  303. #endif
  304. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
  305. #undef CONFIG_CMD_SAVEENV
  306. #undef CONFIG_CMD_LOADS
  307. #endif
  308. #undef CONFIG_WATCHDOG /* watchdog disabled */
  309. /*
  310. * Miscellaneous configurable options
  311. */
  312. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  313. #define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
  314. #if defined(CONFIG_CMD_KGDB)
  315. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  316. #else
  317. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  318. #endif
  319. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  320. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  321. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  322. #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
  323. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  324. /*
  325. * For booting Linux, the board info and command line data
  326. * have to be in the first 8 MB of memory, since this is
  327. * the maximum mapped by the Linux kernel during initialization.
  328. */
  329. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  330. #if defined(CONFIG_CMD_KGDB)
  331. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  332. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  333. #endif
  334. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  335. #define CONFIG_HAS_ETH0
  336. #define CONFIG_HAS_ETH1
  337. #endif
  338. /* You can compile in a MAC address and your custom net settings by using
  339. * the following syntax. Your board should be marked with the assigned
  340. * MAC addresses directly on it.
  341. *
  342. * #define CONFIG_ETHADDR de:ad:be:ef:00:00
  343. * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
  344. * #define CONFIG_SERVERIP <server ip>
  345. * #define CONFIG_IPADDR <board ip>
  346. * #define CONFIG_GATEWAYIP <gateway ip>
  347. * #define CONFIG_NETMASK <your netmask>
  348. */
  349. #define CONFIG_HOSTNAME SBC8560
  350. #define CONFIG_ROOTPATH /home/ppc
  351. #define CONFIG_BOOTFILE uImage
  352. #define CONFIG_EXTRA_ENV_SETTINGS \
  353. "netdev=eth0\0" \
  354. "consoledev=ttyS0\0" \
  355. "ramdiskaddr=2000000\0" \
  356. "ramdiskfile=ramdisk.uboot\0" \
  357. "fdtaddr=c00000\0" \
  358. "fdtfile=sbc8560.dtb\0"
  359. #define CONFIG_NFSBOOTCOMMAND \
  360. "setenv bootargs root=/dev/nfs rw " \
  361. "nfsroot=$serverip:$rootpath " \
  362. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  363. "console=$consoledev,$baudrate $othbootargs;" \
  364. "tftp $loadaddr $bootfile;" \
  365. "tftp $fdtaddr $fdtfile;" \
  366. "bootm $loadaddr - $fdtaddr"
  367. #define CONFIG_RAMBOOTCOMMAND \
  368. "setenv bootargs root=/dev/ram rw " \
  369. "console=$consoledev,$baudrate $othbootargs;" \
  370. "tftp $ramdiskaddr $ramdiskfile;" \
  371. "tftp $loadaddr $bootfile;" \
  372. "tftp $fdtaddr $fdtfile;" \
  373. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  374. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  375. #endif /* __CONFIG_H */