tegra20-tec.dts 1.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. /dts-v1/;
  2. /include/ ARCH_CPU_DTS
  3. / {
  4. model = "Avionic Design Tamonten Evaluation Carrier";
  5. compatible = "ad,tec", "nvidia,tegra20";
  6. aliases {
  7. usb0 = "/usb@c5008000";
  8. };
  9. memory {
  10. reg = <0x00000000 0x20000000>;
  11. };
  12. host1x {
  13. status = "okay";
  14. dc@54200000 {
  15. status = "okay";
  16. rgb {
  17. nvidia,panel = <&lcd_panel>;
  18. status = "okay";
  19. };
  20. };
  21. };
  22. serial@70006300 {
  23. clock-frequency = <216000000>;
  24. };
  25. i2c@7000c000 {
  26. status = "disabled";
  27. };
  28. i2c@7000c400 {
  29. status = "disabled";
  30. };
  31. i2c@7000c500 {
  32. status = "disabled";
  33. };
  34. i2c@7000d000 {
  35. status = "disabled";
  36. };
  37. usb@c5000000 {
  38. status = "disabled";
  39. };
  40. usb@c5004000 {
  41. status = "disabled";
  42. };
  43. nand-controller@70008000 {
  44. nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
  45. nvidia,width = <8>;
  46. nvidia,timing = <26 100 20 80 20 10 12 10 70>;
  47. nand@0 {
  48. reg = <0>;
  49. compatible = "hynix,hy27uf4g2b", "nand-flash";
  50. };
  51. };
  52. lcd_panel: panel {
  53. clock = <33260000>;
  54. xres = <800>;
  55. yres = <480>;
  56. left-margin = <120>;
  57. right-margin = <120>;
  58. hsync-len = <16>;
  59. lower-margin = <15>;
  60. upper-margin = <15>;
  61. vsync-len = <15>;
  62. nvidia,bits-per-pixel = <16>;
  63. nvidia,pwm = <&pwm 0 500000>;
  64. nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
  65. nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
  66. nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
  67. nvidia,panel-timings = <0 0 0 0>;
  68. };
  69. };