tegra20.dtsi 6.2 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. tegra_car: clock@60006000 {
  6. compatible = "nvidia,tegra20-car";
  7. reg = <0x60006000 0x1000>;
  8. #clock-cells = <1>;
  9. };
  10. intc: interrupt-controller@50041000 {
  11. compatible = "nvidia,tegra20-gic";
  12. interrupt-controller;
  13. #interrupt-cells = <1>;
  14. reg = < 0x50041000 0x1000 >,
  15. < 0x50040100 0x0100 >;
  16. };
  17. i2c@7000c000 {
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. compatible = "nvidia,tegra20-i2c";
  21. reg = <0x7000C000 0x100>;
  22. interrupts = < 70 >;
  23. /* PERIPH_ID_I2C1, PLL_P_OUT3 */
  24. clocks = <&tegra_car 12>, <&tegra_car 124>;
  25. };
  26. i2c@7000c400 {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. compatible = "nvidia,tegra20-i2c";
  30. reg = <0x7000C400 0x100>;
  31. interrupts = < 116 >;
  32. /* PERIPH_ID_I2C2, PLL_P_OUT3 */
  33. clocks = <&tegra_car 54>, <&tegra_car 124>;
  34. };
  35. i2c@7000c500 {
  36. #address-cells = <1>;
  37. #size-cells = <0>;
  38. compatible = "nvidia,tegra20-i2c";
  39. reg = <0x7000C500 0x100>;
  40. interrupts = < 124 >;
  41. /* PERIPH_ID_I2C3, PLL_P_OUT3 */
  42. clocks = <&tegra_car 67>, <&tegra_car 124>;
  43. };
  44. i2c@7000d000 {
  45. #address-cells = <1>;
  46. #size-cells = <0>;
  47. compatible = "nvidia,tegra20-i2c-dvc";
  48. reg = <0x7000D000 0x200>;
  49. interrupts = < 85 >;
  50. /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
  51. clocks = <&tegra_car 47>, <&tegra_car 124>;
  52. };
  53. i2s@70002800 {
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. compatible = "nvidia,tegra20-i2s";
  57. reg = <0x70002800 0x200>;
  58. interrupts = < 45 >;
  59. dma-channel = < 2 >;
  60. };
  61. i2s@70002a00 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. compatible = "nvidia,tegra20-i2s";
  65. reg = <0x70002a00 0x200>;
  66. interrupts = < 35 >;
  67. dma-channel = < 1 >;
  68. };
  69. das@70000c00 {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. compatible = "nvidia,tegra20-das";
  73. reg = <0x70000c00 0x80>;
  74. };
  75. gpio: gpio@6000d000 {
  76. compatible = "nvidia,tegra20-gpio";
  77. reg = < 0x6000d000 0x1000 >;
  78. interrupts = < 64 65 66 67 87 119 121 >;
  79. #gpio-cells = <2>;
  80. gpio-controller;
  81. };
  82. pinmux: pinmux@70000000 {
  83. compatible = "nvidia,tegra20-pinmux";
  84. reg = < 0x70000014 0x10 /* Tri-state registers */
  85. 0x70000080 0x20 /* Mux registers */
  86. 0x700000a0 0x14 /* Pull-up/down registers */
  87. 0x70000868 0xa8 >; /* Pad control registers */
  88. };
  89. serial@70006000 {
  90. compatible = "nvidia,tegra20-uart";
  91. reg = <0x70006000 0x40>;
  92. reg-shift = <2>;
  93. interrupts = < 68 >;
  94. };
  95. serial@70006040 {
  96. compatible = "nvidia,tegra20-uart";
  97. reg = <0x70006040 0x40>;
  98. reg-shift = <2>;
  99. interrupts = < 69 >;
  100. };
  101. serial@70006200 {
  102. compatible = "nvidia,tegra20-uart";
  103. reg = <0x70006200 0x100>;
  104. reg-shift = <2>;
  105. interrupts = < 78 >;
  106. };
  107. serial@70006300 {
  108. compatible = "nvidia,tegra20-uart";
  109. reg = <0x70006300 0x100>;
  110. reg-shift = <2>;
  111. interrupts = < 122 >;
  112. };
  113. serial@70006400 {
  114. compatible = "nvidia,tegra20-uart";
  115. reg = <0x70006400 0x100>;
  116. reg-shift = <2>;
  117. interrupts = < 123 >;
  118. };
  119. sdhci@c8000000 {
  120. compatible = "nvidia,tegra20-sdhci";
  121. reg = <0xc8000000 0x200>;
  122. interrupts = < 46 >;
  123. };
  124. sdhci@c8000200 {
  125. compatible = "nvidia,tegra20-sdhci";
  126. reg = <0xc8000200 0x200>;
  127. interrupts = < 47 >;
  128. };
  129. sdhci@c8000400 {
  130. compatible = "nvidia,tegra20-sdhci";
  131. reg = <0xc8000400 0x200>;
  132. interrupts = < 51 >;
  133. };
  134. sdhci@c8000600 {
  135. compatible = "nvidia,tegra20-sdhci";
  136. reg = <0xc8000600 0x200>;
  137. interrupts = < 63 >;
  138. };
  139. usb@c5000000 {
  140. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  141. reg = <0xc5000000 0x4000>;
  142. interrupts = < 52 >;
  143. phy_type = "utmi";
  144. clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
  145. nvidia,has-legacy-mode;
  146. };
  147. usb@c5004000 {
  148. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  149. reg = <0xc5004000 0x4000>;
  150. interrupts = < 53 >;
  151. phy_type = "ulpi";
  152. clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
  153. };
  154. usb@c5008000 {
  155. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  156. reg = <0xc5008000 0x4000>;
  157. interrupts = < 129 >;
  158. phy_type = "utmi";
  159. clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
  160. };
  161. emc@7000f400 {
  162. #address-cells = < 1 >;
  163. #size-cells = < 0 >;
  164. compatible = "nvidia,tegra20-emc";
  165. reg = <0x7000f400 0x200>;
  166. };
  167. kbc@7000e200 {
  168. compatible = "nvidia,tegra20-kbc";
  169. reg = <0x7000e200 0x0078>;
  170. };
  171. nand: nand-controller@70008000 {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. compatible = "nvidia,tegra20-nand";
  175. reg = <0x70008000 0x100>;
  176. };
  177. pwm: pwm@7000a000 {
  178. compatible = "nvidia,tegra20-pwm";
  179. reg = <0x7000a000 0x100>;
  180. #pwm-cells = <2>;
  181. };
  182. host1x {
  183. compatible = "nvidia,tegra20-host1x", "simple-bus";
  184. reg = <0x50000000 0x00024000>;
  185. interrupts = <0 65 0x04 /* mpcore syncpt */
  186. 0 67 0x04>; /* mpcore general */
  187. status = "disabled";
  188. #address-cells = <1>;
  189. #size-cells = <1>;
  190. ranges = <0x54000000 0x54000000 0x04000000>;
  191. /* video-encoding/decoding */
  192. mpe {
  193. reg = <0x54040000 0x00040000>;
  194. interrupts = <0 68 0x04>;
  195. status = "disabled";
  196. };
  197. /* video input */
  198. vi {
  199. reg = <0x54080000 0x00040000>;
  200. interrupts = <0 69 0x04>;
  201. status = "disabled";
  202. };
  203. /* EPP */
  204. epp {
  205. reg = <0x540c0000 0x00040000>;
  206. interrupts = <0 70 0x04>;
  207. status = "disabled";
  208. };
  209. /* ISP */
  210. isp {
  211. reg = <0x54100000 0x00040000>;
  212. interrupts = <0 71 0x04>;
  213. status = "disabled";
  214. };
  215. /* 2D engine */
  216. gr2d {
  217. reg = <0x54140000 0x00040000>;
  218. interrupts = <0 72 0x04>;
  219. status = "disabled";
  220. };
  221. /* 3D engine */
  222. gr3d {
  223. reg = <0x54180000 0x00040000>;
  224. status = "disabled";
  225. };
  226. /* display controllers */
  227. dc@54200000 {
  228. compatible = "nvidia,tegra20-dc";
  229. reg = <0x54200000 0x00040000>;
  230. interrupts = <0 73 0x04>;
  231. status = "disabled";
  232. rgb {
  233. status = "disabled";
  234. };
  235. };
  236. dc@54240000 {
  237. compatible = "nvidia,tegra20-dc";
  238. reg = <0x54240000 0x00040000>;
  239. interrupts = <0 74 0x04>;
  240. status = "disabled";
  241. rgb {
  242. status = "disabled";
  243. };
  244. };
  245. /* outputs */
  246. hdmi {
  247. compatible = "nvidia,tegra20-hdmi";
  248. reg = <0x54280000 0x00040000>;
  249. interrupts = <0 75 0x04>;
  250. status = "disabled";
  251. };
  252. tvo {
  253. compatible = "nvidia,tegra20-tvo";
  254. reg = <0x542c0000 0x00040000>;
  255. interrupts = <0 76 0x04>;
  256. status = "disabled";
  257. };
  258. dsi {
  259. compatible = "nvidia,tegra20-dsi";
  260. reg = <0x54300000 0x00040000>;
  261. status = "disabled";
  262. };
  263. };
  264. };