M5235EVB.h 7.5 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF5329 FireEngine board.
  3. *
  4. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * board/config.h - configuration options, board specific
  27. */
  28. #ifndef _M5235EVB_H
  29. #define _M5235EVB_H
  30. /*
  31. * High Level Configuration Options
  32. * (easy to change)
  33. */
  34. #define CONFIG_MCF523x /* define processor family */
  35. #define CONFIG_M5235 /* define processor type */
  36. #define CONFIG_MCFUART
  37. #define CFG_UART_PORT (0)
  38. #define CONFIG_BAUDRATE 115200
  39. #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  40. #undef CONFIG_WATCHDOG
  41. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  42. /*
  43. * BOOTP options
  44. */
  45. #define CONFIG_BOOTP_BOOTFILESIZE
  46. #define CONFIG_BOOTP_BOOTPATH
  47. #define CONFIG_BOOTP_GATEWAY
  48. #define CONFIG_BOOTP_HOSTNAME
  49. /* Command line configuration */
  50. #include <config_cmd_default.h>
  51. #define CONFIG_CMD_BOOTD
  52. #define CONFIG_CMD_CACHE
  53. #define CONFIG_CMD_DHCP
  54. #define CONFIG_CMD_ELF
  55. #define CONFIG_CMD_FLASH
  56. #define CONFIG_CMD_I2C
  57. #define CONFIG_CMD_MEMORY
  58. #define CONFIG_CMD_MISC
  59. #define CONFIG_CMD_MII
  60. #define CONFIG_CMD_NET
  61. #define CONFIG_CMD_PCI
  62. #define CONFIG_CMD_PING
  63. #define CONFIG_CMD_REGINFO
  64. #undef CONFIG_CMD_LOADB
  65. #undef CONFIG_CMD_LOADS
  66. #define CONFIG_MCFFEC
  67. #ifdef CONFIG_MCFFEC
  68. # define CONFIG_NET_MULTI 1
  69. # define CONFIG_MII 1
  70. # define CFG_DISCOVER_PHY
  71. # define CFG_RX_ETH_BUFFER 8
  72. # define CFG_FAULT_ECHO_LINK_DOWN
  73. # define CFG_FEC0_PINMUX 0
  74. # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
  75. # define MCFFEC_TOUT_LOOP 50000
  76. /* If CFG_DISCOVER_PHY is not defined - hardcoded */
  77. # ifndef CFG_DISCOVER_PHY
  78. # define FECDUPLEX FULL
  79. # define FECSPEED _100BASET
  80. # else
  81. # ifndef CFG_FAULT_ECHO_LINK_DOWN
  82. # define CFG_FAULT_ECHO_LINK_DOWN
  83. # endif
  84. # endif /* CFG_DISCOVER_PHY */
  85. #endif
  86. /* Timer */
  87. #define CONFIG_MCFTMR
  88. #undef CONFIG_MCFPIT
  89. /* I2C */
  90. #define CONFIG_FSL_I2C
  91. #define CONFIG_HARD_I2C /* I2C with hw support */
  92. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  93. #define CFG_I2C_SPEED 80000
  94. #define CFG_I2C_SLAVE 0x7F
  95. #define CFG_I2C_OFFSET 0x00000300
  96. #define CFG_IMMR CFG_MBAR
  97. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  98. #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
  99. #define CONFIG_BOOTFILE "u-boot.bin"
  100. #ifdef CONFIG_MCFFEC
  101. # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
  102. # define CONFIG_IPADDR 192.162.1.2
  103. # define CONFIG_NETMASK 255.255.255.0
  104. # define CONFIG_SERVERIP 192.162.1.1
  105. # define CONFIG_GATEWAYIP 192.162.1.1
  106. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  107. #endif /* FEC_ENET */
  108. #define CONFIG_HOSTNAME M5235EVB
  109. #define CONFIG_EXTRA_ENV_SETTINGS \
  110. "netdev=eth0\0" \
  111. "loadaddr=10000\0" \
  112. "u-boot=u-boot.bin\0" \
  113. "load=tftp ${loadaddr) ${u-boot}\0" \
  114. "upd=run load; run prog\0" \
  115. "prog=prot off ffe00000 ffe3ffff;" \
  116. "era ffe00000 ffe3ffff;" \
  117. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  118. "save\0" \
  119. ""
  120. #define CONFIG_PRAM 512 /* 512 KB */
  121. #define CFG_PROMPT "-> "
  122. #define CFG_LONGHELP /* undef to save memory */
  123. #if defined(CONFIG_KGDB)
  124. # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  125. #else
  126. # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  127. #endif
  128. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  129. #define CFG_MAXARGS 16 /* max number of command args */
  130. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  131. #define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
  132. #define CFG_HZ 1000
  133. #define CFG_CLK 75000000
  134. #define CFG_CPU_CLK CFG_CLK * 2
  135. #define CFG_MBAR 0x40000000
  136. /*
  137. * Low Level Configuration Settings
  138. * (address mappings, register initial values, etc.)
  139. * You should know what you are doing if you make changes here.
  140. */
  141. /*-----------------------------------------------------------------------
  142. * Definitions for initial stack pointer and data area (in DPRAM)
  143. */
  144. #define CFG_INIT_RAM_ADDR 0x20000000
  145. #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
  146. #define CFG_INIT_RAM_CTRL 0x21
  147. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  148. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
  149. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  150. /*-----------------------------------------------------------------------
  151. * Start addresses for the final memory configuration
  152. * (Set up by the startup code)
  153. * Please note that CFG_SDRAM_BASE _must_ start at 0
  154. */
  155. #define CFG_SDRAM_BASE 0x00000000
  156. #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
  157. #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
  158. #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
  159. #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
  160. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  161. #define CFG_BOOTPARAMS_LEN 64*1024
  162. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  163. /*
  164. * For booting Linux, the board info and command line data
  165. * have to be in the first 8 MB of memory, since this is
  166. * the maximum mapped by the Linux kernel during initialization ??
  167. */
  168. /* Initial Memory map for Linux */
  169. #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
  170. /*-----------------------------------------------------------------------
  171. * FLASH organization
  172. */
  173. #define CFG_FLASH_CFI
  174. #ifdef CFG_FLASH_CFI
  175. # define CFG_FLASH_CFI_DRIVER 1
  176. # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
  177. #ifdef NORFLASH_PS32BIT
  178. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  179. #else
  180. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  181. #endif
  182. # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  183. # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  184. # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  185. #endif
  186. #define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
  187. /* Configuration for environment
  188. * Environment is embedded in u-boot in the second sector of the flash
  189. */
  190. #define CFG_ENV_IS_IN_FLASH 1
  191. #define CFG_ENV_IS_EMBEDDED 1
  192. #ifdef NORFLASH_PS32BIT
  193. # define CFG_ENV_OFFSET (0x8000)
  194. # define CFG_ENV_SIZE 0x4000
  195. # define CFG_ENV_SECT_SIZE 0x4000
  196. #else
  197. # define CFG_ENV_OFFSET (0x4000)
  198. # define CFG_ENV_SIZE 0x2000
  199. # define CFG_ENV_SECT_SIZE 0x2000
  200. #endif
  201. /*-----------------------------------------------------------------------
  202. * Cache Configuration
  203. */
  204. #define CFG_CACHELINE_SIZE 16
  205. /*-----------------------------------------------------------------------
  206. * Chipselect bank definitions
  207. */
  208. /*
  209. * CS0 - NOR Flash 1, 2, 4, or 8MB
  210. * CS1 - Available
  211. * CS2 - Available
  212. * CS3 - Available
  213. * CS4 - Available
  214. * CS5 - Available
  215. * CS6 - Available
  216. * CS7 - Available
  217. */
  218. #ifdef NORFLASH_PS32BIT
  219. # define CFG_CS0_BASE 0xFFC0
  220. # define CFG_CS0_MASK 0x003f0001
  221. # define CFG_CS0_CTRL 0x1D00
  222. #else
  223. # define CFG_CS0_BASE 0xFFE0
  224. # define CFG_CS0_MASK 0x001f0001
  225. # define CFG_CS0_CTRL 0x1D80
  226. #endif
  227. #endif /* _M5329EVB_H */