jedec_flash.c 8.1 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Michael Schwingen, <michael@schwingen.org>
  4. *
  5. * based in great part on jedec_probe.c from linux kernel:
  6. * (C) 2000 Red Hat. GPL'd.
  7. * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. *
  27. */
  28. /* The DEBUG define must be before common to enable debugging */
  29. /*#define DEBUG*/
  30. #include <common.h>
  31. #include <asm/processor.h>
  32. #include <asm/io.h>
  33. #include <asm/byteorder.h>
  34. #include <environment.h>
  35. #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
  36. /* Manufacturers */
  37. #define MANUFACTURER_AMD 0x0001
  38. #define MANUFACTURER_SST 0x00BF
  39. /* AMD */
  40. #define AM29DL800BB 0x22CB
  41. #define AM29DL800BT 0x224A
  42. #define AM29F800BB 0x2258
  43. #define AM29F800BT 0x22D6
  44. #define AM29LV400BB 0x22BA
  45. #define AM29LV400BT 0x22B9
  46. #define AM29LV800BB 0x225B
  47. #define AM29LV800BT 0x22DA
  48. #define AM29LV160DT 0x22C4
  49. #define AM29LV160DB 0x2249
  50. #define AM29F017D 0x003D
  51. #define AM29F016D 0x00AD
  52. #define AM29F080 0x00D5
  53. #define AM29F040 0x00A4
  54. #define AM29LV040B 0x004F
  55. #define AM29F032B 0x0041
  56. #define AM29F002T 0x00B0
  57. /* SST */
  58. #define SST39LF800 0x2781
  59. #define SST39LF160 0x2782
  60. #define SST39VF1601 0x234b
  61. #define SST39LF512 0x00D4
  62. #define SST39LF010 0x00D5
  63. #define SST39LF020 0x00D6
  64. #define SST39LF040 0x00D7
  65. #define SST39SF010A 0x00B5
  66. #define SST39SF020A 0x00B6
  67. /*
  68. * Unlock address sets for AMD command sets.
  69. * Intel command sets use the MTD_UADDR_UNNECESSARY.
  70. * Each identifier, except MTD_UADDR_UNNECESSARY, and
  71. * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
  72. * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
  73. * initialization need not require initializing all of the
  74. * unlock addresses for all bit widths.
  75. */
  76. enum uaddr {
  77. MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
  78. MTD_UADDR_0x0555_0x02AA,
  79. MTD_UADDR_0x0555_0x0AAA,
  80. MTD_UADDR_0x5555_0x2AAA,
  81. MTD_UADDR_0x0AAA_0x0555,
  82. MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
  83. MTD_UADDR_UNNECESSARY, /* Does not require any address */
  84. };
  85. struct unlock_addr {
  86. u32 addr1;
  87. u32 addr2;
  88. };
  89. /*
  90. * I don't like the fact that the first entry in unlock_addrs[]
  91. * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
  92. * should not be used. The problem is that structures with
  93. * initializers have extra fields initialized to 0. It is _very_
  94. * desireable to have the unlock address entries for unsupported
  95. * data widths automatically initialized - that means that
  96. * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
  97. * must go unused.
  98. */
  99. static const struct unlock_addr unlock_addrs[] = {
  100. [MTD_UADDR_NOT_SUPPORTED] = {
  101. .addr1 = 0xffff,
  102. .addr2 = 0xffff
  103. },
  104. [MTD_UADDR_0x0555_0x02AA] = {
  105. .addr1 = 0x0555,
  106. .addr2 = 0x02aa
  107. },
  108. [MTD_UADDR_0x0555_0x0AAA] = {
  109. .addr1 = 0x0555,
  110. .addr2 = 0x0aaa
  111. },
  112. [MTD_UADDR_0x5555_0x2AAA] = {
  113. .addr1 = 0x5555,
  114. .addr2 = 0x2aaa
  115. },
  116. [MTD_UADDR_0x0AAA_0x0555] = {
  117. .addr1 = 0x0AAA,
  118. .addr2 = 0x0555
  119. },
  120. [MTD_UADDR_DONT_CARE] = {
  121. .addr1 = 0x0000, /* Doesn't matter which address */
  122. .addr2 = 0x0000 /* is used - must be last entry */
  123. },
  124. [MTD_UADDR_UNNECESSARY] = {
  125. .addr1 = 0x0000,
  126. .addr2 = 0x0000
  127. }
  128. };
  129. struct amd_flash_info {
  130. const __u16 mfr_id;
  131. const __u16 dev_id;
  132. const char *name;
  133. const int DevSize;
  134. const int NumEraseRegions;
  135. const int CmdSet;
  136. const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
  137. const ulong regions[6];
  138. };
  139. #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
  140. #define SIZE_64KiB 16
  141. #define SIZE_128KiB 17
  142. #define SIZE_256KiB 18
  143. #define SIZE_512KiB 19
  144. #define SIZE_1MiB 20
  145. #define SIZE_2MiB 21
  146. #define SIZE_4MiB 22
  147. #define SIZE_8MiB 23
  148. static const struct amd_flash_info jedec_table[] = {
  149. #ifdef CFG_FLASH_LEGACY_256Kx8
  150. {
  151. .mfr_id = MANUFACTURER_SST,
  152. .dev_id = SST39LF020,
  153. .name = "SST 39LF020",
  154. .uaddr = {
  155. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  156. },
  157. .DevSize = SIZE_256KiB,
  158. .CmdSet = P_ID_AMD_STD,
  159. .NumEraseRegions= 1,
  160. .regions = {
  161. ERASEINFO(0x01000,64),
  162. }
  163. },
  164. #endif
  165. #ifdef CFG_FLASH_LEGACY_512Kx8
  166. {
  167. .mfr_id = MANUFACTURER_AMD,
  168. .dev_id = AM29LV040B,
  169. .name = "AMD AM29LV040B",
  170. .uaddr = {
  171. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  172. },
  173. .DevSize = SIZE_512KiB,
  174. .CmdSet = P_ID_AMD_STD,
  175. .NumEraseRegions= 1,
  176. .regions = {
  177. ERASEINFO(0x10000,8),
  178. }
  179. },
  180. {
  181. .mfr_id = MANUFACTURER_SST,
  182. .dev_id = SST39LF040,
  183. .name = "SST 39LF040",
  184. .uaddr = {
  185. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  186. },
  187. .DevSize = SIZE_512KiB,
  188. .CmdSet = P_ID_AMD_STD,
  189. .NumEraseRegions= 1,
  190. .regions = {
  191. ERASEINFO(0x01000,128),
  192. }
  193. },
  194. #endif
  195. #ifdef CFG_FLASH_LEGACY_512Kx16
  196. {
  197. .mfr_id = MANUFACTURER_AMD,
  198. .dev_id = AM29LV400BB,
  199. .name = "AMD AM29LV400BB",
  200. .uaddr = {
  201. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  202. },
  203. .DevSize = SIZE_512KiB,
  204. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  205. .NumEraseRegions= 4,
  206. .regions = {
  207. ERASEINFO(0x04000,1),
  208. ERASEINFO(0x02000,2),
  209. ERASEINFO(0x08000,1),
  210. ERASEINFO(0x10000,7),
  211. }
  212. },
  213. #endif
  214. };
  215. static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
  216. {
  217. int i,j;
  218. int sect_cnt;
  219. int size_ratio;
  220. int total_size;
  221. enum uaddr uaddr_idx;
  222. size_ratio = info->portwidth / info->chipwidth;
  223. debug("Found JEDEC Flash: %s\n", jedec_entry->name);
  224. info->vendor = jedec_entry->CmdSet;
  225. /* Todo: do we need device-specific timeouts? */
  226. info->erase_blk_tout = 30000;
  227. info->buffer_write_tout = 1000;
  228. info->write_tout = 100;
  229. info->name = jedec_entry->name;
  230. /* copy unlock addresses from device table to CFI info struct. This
  231. is just here because the addresses are in the table anyway - if
  232. the flash is not detected due to wrong unlock addresses,
  233. flash_detect_legacy would have to try all of them before we even
  234. get here. */
  235. switch(info->chipwidth) {
  236. case FLASH_CFI_8BIT:
  237. uaddr_idx = jedec_entry->uaddr[0];
  238. break;
  239. case FLASH_CFI_16BIT:
  240. uaddr_idx = jedec_entry->uaddr[1];
  241. break;
  242. case FLASH_CFI_32BIT:
  243. uaddr_idx = jedec_entry->uaddr[2];
  244. break;
  245. default:
  246. uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
  247. break;
  248. }
  249. debug("unlock address index %d\n", uaddr_idx);
  250. info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
  251. info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
  252. debug("unlock addresses are 0x%x/0x%x\n", info->addr_unlock1, info->addr_unlock2);
  253. sect_cnt = 0;
  254. total_size = 0;
  255. for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
  256. ulong erase_region_size = jedec_entry->regions[i] >> 8;
  257. ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
  258. total_size += erase_region_size * erase_region_count;
  259. debug ("erase_region_count = %d erase_region_size = %d\n",
  260. erase_region_count, erase_region_size);
  261. for (j = 0; j < erase_region_count; j++) {
  262. if (sect_cnt >= CFG_MAX_FLASH_SECT) {
  263. printf("ERROR: too many flash sectors\n");
  264. break;
  265. }
  266. info->start[sect_cnt] = base;
  267. base += (erase_region_size * size_ratio);
  268. sect_cnt++;
  269. }
  270. }
  271. info->sector_count = sect_cnt;
  272. info->size = total_size * size_ratio;
  273. }
  274. /*-----------------------------------------------------------------------
  275. * match jedec ids against table. If a match is found, fill flash_info entry
  276. */
  277. int jedec_flash_match(flash_info_t *info, ulong base)
  278. {
  279. int ret = 0;
  280. int i;
  281. ulong mask = 0xFFFF;
  282. if (info->chipwidth == 1)
  283. mask = 0xFF;
  284. for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
  285. if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
  286. (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
  287. fill_info(info, &jedec_table[i], base);
  288. ret = 1;
  289. break;
  290. }
  291. }
  292. return ret;
  293. }